Kabushiki Kaisha Toshiba

Yoshitomo Sagae

Toshiki Seshita

Ryoichi Ohara

Masanori Ochi

Fumio Sasaki

Akira Yoshioka

Hidetoshi Fujimoto

Mitsuru Sugawara

Masayuki Sugiura

Takao Noda

Tetsuro Nozu

Kazuya Nishihori

Yugo Kunishi

Yoshio Itagaki

Hirotsugu Wakimoto

Toshiyuki Shimizu

Kenji Hommyo

Noriyasu Kurihara

A semiconductor device includes a SOI substrate including a silicon substrate, an oxide layer on the silicon substrate, and a silicon layer on the oxide layer; a source region and a drain region formed in the silicon layer; and an acceptor-doped layer formed between the oxide layer and the silicon substrate, the acceptor-doped layer being doped with acceptors.

SOI substrate with acceptor-doped layer

According to one embodiment, a semiconductor switch includes a voltage generator, a voltage controller, a driver, and a switch unit. The voltage generator generates a negative first potential. The voltage controller controls the first potential according to a terminal switch signal input from an outside. The driver is input the terminal switch signal, and outputs at least one selected from the first potential and the second potential based on the terminal switch signal. The second potential is a power supply voltage or is higher than the power supply voltage. The switch unit is provided on an SOT substrate, switches a connection between an antenna terminal and any one of high frequency terminals based on the output of the driver.

Semiconductor switch and wireless device

According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

High-frequency switch

A semiconductor switch includes: a first terminal; a second terminal; a switch section including a through FET connected between the first terminal and the second terminal and a shunt FET connected between the second terminal and a first ground terminal; a first control terminal configured to drive the through FET; a second control terminal configured to drive the shunt FET; and a driver provided on a substrate together with the switch section and configured to provide a differential output to the first control terminal and the second control terminal.

Semiconductor switch

A semiconductor device receiving as input a radio frequency signal having a frequency of 500 MHz or more and a power of 20 dBm or more is provided. The semiconductor device includes: a silicon substrate; a silicon oxide film formed on the silicon substrate; a radio frequency interconnect provided on the silicon oxide film and passing the radio frequency signal; a fixed potential interconnect provided on the silicon oxide film and placed at a fixed potential; and an acceptor-doped layer. The acceptor-doped layer is formed in a region of the silicon substrate. The region is in contact with the silicon oxide film. The acceptor-doped layer is doped with acceptors.

Radio frequency semiconductor device

A semiconductor device comprises a semiconductor switching element having a first electrode, a second electrode and a third electrode, and permitting a high-frequency signal to pass through between the first electrode and the second electrode, depending upon the potential of the third electrode, bias voltages at the first and second electrodes being substantially equal; and an inductor element and a capacitor element which are connected in parallel with respect to the semiconductor switching element at the first and second electrodes and are connected in series to each other.

Semiconductor device, communication device, and semiconductor device inspecting method

A bipolar transistor is provided which includes a GaAs substrate, an n-type collector region formed on the GaAs substrate, a p-type base region formed on the n-type collector region and having a p-type base layer of SiGe having a composition lattice-matched with the GaAs substrate, and an n-type emitter region formed on the p-type base region. A bipolar transistor may include a GaAs substrate, a collector region of a first conductivity type formed on the GaAs substrate and including a collector contact layer of the first conductivity type SiGe, which has a composition lattice-matched with the GaAs substrate, a base region of a second conductivity type formed on the collector region of the first conductivity type, and an emitter region of the first conductivity type formed on the base region of the second conductivity type.

Bipolar transistor with a GaAs substrate and a SiGe base or collector

The invention discloses a semiconductor switching circuit suitable for a Single Pole n Throw (SPnT) switching circuit having: a common terminal; first through third terminals, ground and control terminals, through FETS, shunt FETs, wherein when a first electric potential is supplied only to a Jth control terminal, and a second lower electric potential is supplied to the other control terminals, the common and Jth terminals are electrically connected and the first through third terminals are electrically disconnected.

Semiconductor switching circuit

A heterojunction type compound semiconductor field effect transistor includes a channel layer, a first electron supply layer, an electric field strength reducing layer, a first contact layer, a recess stopper layer, and a second contact layer sequentially stacked on a compound semiconductor substrate. This transistor has a double recess structure. The first contact layer is composed of GaAs or InGaAs doped with n type impurities with a high electron mobility. The electric field strength reducing layer is composed of intrinsic InGaP.

Growing community of inventors

Kanagawa-ken, Japan

Yoshitomo Sagae