Renesas Electronics Corporation

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi, Ltd.

Yoshito Nakazawa

Yuji Yatsuda

Hitoshi Matsuura

Tomohiro Tamaki

Sakae Kubo

Kentaro Oishi

Masayoshi Kobayashi

Satoshi Kudo

Sumito Numazawa

Yasuo Imai

Takashi Shigematsu

Akihiro Ohnishi

Kozo Uesawa

Nobuyoshi Matsuura

Tsuyoshi Kachi

Nobuyuki Shirai

Satoshi Eguchi

Daisuke Arai

Tomoaki Uno

Makoto Koshimizu

Yoshinori Hoshino

Tomohiro Imai

Ikuo Hara

Tsuyoshi Tabata

Atsushi Shinbori

Yukio Takahashi

Masaki Shiraishi

Katsumi Eikyu

Kozo Sakamoto

Atsushi Fujiki

Hirokatsu Suzuki

Shigeaki Saito

Shunichi Yamauchi

Eiji Yanokura

Norio Hosoya

A semiconductor device according to one embodiment includes an IGBT having a p-type collector layer and an n-type field stop layer on a back surface of a silicon substrate. The n-type field stop layer is selectively provided on an upper side of the p-type collector layer such that a first end portion of the n-type field stop layer is separated from a first side surface of the silicon substrate by a predetermined distance, and an n-type drift layer is provided between the first side surface of the silicon substrate and the first end portion of the n-type field stop layer. An impurity concentration of the n-type drift layer is lower than an impurity concentration of the n-type field stop layer.

Semiconductor device and method of manufacturing the same

An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.

A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.

Trench gate semiconductor device with dummy gate electrode and manufacturing method of the same

A semiconductor device includes: a cell region provided in a main surface of a semiconductor substrate composed of a crystal plane (100); a field insulating film embedded in the semiconductor substrate; and an annular p-type well region surrounding the cell region. The p-type well region includes a first region extending in a &#x3c;010&#x3e; direction, a second region extending in a &#x3c;001&#x3e; direction, and a third region connecting the first region and the second region and having an arc shape in plan view. The field insulating film has an opening provided in the p-type well region and extending along the p-type well region in plan view. The opening includes a first opening extending in the &#x3c;010&#x3e; direction in the first region and a second opening extending in the &#x3c;001&#x3e; direction in the second region, and the first opening and the second opening are divided from each other in the third region.

Semiconductor device

The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation &#x3c;011&#x3e;. Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation &#x3c;011&#x3e;, and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation &#x3c;010&#x3e; and the crystal orientation &#x3c;011&#x3e;.

Semiconductor device and manufacturing method of the same

A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a ppolysilicon gate electrode and a pfield plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.

Method of manufacturing a P-channel power MOSFET

A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Power semiconductor device

A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Power superjunction MOSFET device with resurf regions

A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising the steps of (a) providing a semiconductor substrate including a first epitaxial layer of a first conductivity type formed over a main surface thereof, (b) doping a lower band gap impurity for making the band gap smaller than the band gap of the first epitaxial layer before doping into the first epitaxial layer in the cell region, and thereby forming a lower band gap region, (c) after the step (b), forming a plurality of first column regions of a second conductivity type which is the opposite conductivity type to the first conductivity type in such a manner as to be separated from one another in the first epitaxial layer extending from the cell region to the peripheral region, and (d) after the step (c), forming a second epitaxial layer.

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Semiconductor device including a MOSFET and having a super-junction structure

In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N-type drift region. The N-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N-type drift region.

IGBT and diode

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Growing community of inventors

Tokyo, Japan

Yoshito Nakazawa