Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Yoshito Nakaoka

Kiyohiro Furutani

Mikio Asakura

Tsukasa Ooishi

Hideto Hidaka

Kei Hamade

Masaki Tsukude

Kyoji Yamasaki

Masaru Haraguchi

Toru Shiomi

Shinji Kawai

Yoshitsugu Dohi

Kazuhiko Takami

A bare chip includes a first semiconductor storage part and a second semiconductor storage part, formed in the stage of a wafer serving as a semiconductor material, capable of storing data independently of each other, and an electric wire serving as a semiconductor storage part employment/nonemployment selection circuit setting each of the first semiconductor storage part and the second semiconductor storage part in either a mode capable of inputting/outputting data or a mode incapable of inputting/outputting the data. Thus obtained is a semiconductor memory module formed by a plurality of bare chips integrally coated with molding resin, having a function of replacing a bare chip detected as defective with a spare chip.

Semiconductor memory module

Data of a plurality of memory cells are read on a plurality of first data lines and combined by a combination/rewrite circuit and transmitted on a second data line and the combined data is written back to the first data line. In combining data, the combination/rewrite circuit performs an addition. Mirrored data can be improved in reliability and a function of correcting an error of the mirror data can also be implemented.

Semiconductor memory having mirroring function

A sense amplifier is connected to a pair of folded bit lines via selection gates. At the time of reading data in a memory cell connected to the bit line, the pair of folded bit lines enter a floating state. At this time, the selection gate is turned off to disconnect the bit line from a sense node. After that, a potential is supplied to the bit line from an equalizer. Consequently, a semiconductor memory device of the invention can suppress deterioration in charge holding capability of a memory cell and prevent erroneous operation.

Semiconductor memory device having sense amplifier

A redundancy determining unit pre-stores a defective memory cell address in a normal memory cell array, and selects a redundant memory cell instead of a normal memory cell in a normal operational mode. The redundancy determining unit selects a designated redundant memory cell row in response to an address signal when a test mode signal and a redundancy identification address signal are activated. If the test mode signal is activated whereas the redundancy identification address signal is inactivated, a replacement operation for the normal memory cell and the redundant memory cell is stopped.

Semiconductor memory device capable of independent selection of normal and redundant memory cells after programming of redundant address

A semiconductor memory device is provided for reducing or preventing any switching to a special mode from a normal mode operation due to noise on an external clock without affecting any access time of the semiconductor memory device. In the semiconductor memory device, input buffer amplifiers converts a plurality of external clock signals into a plurality of internal clock signals each having an internal signal level, respectively, and then, a control clock signal generating circuit generates a control clock signal for controlling an operation of the semiconductor memory device in accordance with the plurality of internal clock signals. At least one of special mode input buffer amplifiers and noise filters has a time response characteristic gently changing according to a change in an input signal, and generates an internal clock signal for a different special mode from a normal mode associated with either one of reading and writing of data from and in the semiconductor memory device in accordance with at least one of the plurality of external clock signals.

Semiconductor memory device provided with generating means for internal clock signal for special mode

In a circuit in which a step-up potential is generated by a charge pump, a through current passing through a buffer circuit (,) when an activation signal (ACTL) is at its low level, can be reduced by arranging so that a detector (,) is ahead of another detector (,) in detecting a decrease in step-up potential V,.

Semiconductor device

A semiconductor integrated circuit having a standard pair of complementary data lines subjected to ternary control, through which data complementary to each other are transmitted when valid data are transmitted, single data lines subjected to binary control, through which data of the same system as that of the pair of complementary data lines are transmitted and a circuit for detecting valid data in a standard intermediate latch circuit which detects an event that the data transmitted through the standard pair of complementary data lines are changed to data complementary to each other, wherein the circuit for detecting valid data confirms arrival of the valid data and controls data corresponding to the data transmitted through the single data lines, to thereby reduce the number of pairs of data lines for narrowing an wiring area of the data lines and reducing a chip size while maintaining a high speed operation.

Semiconductor integrated circuit

Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

Semiconductor memory device having data input/output circuit of small

The potential of a data line is precharged to an H level by a P channel MOS transistor rendered conductive by a precharge signal. The potential of the data line is not driven by a differential amplifier circuit until the difference between the potential of the output of the differential amplifier circuit providing a corresponding signal and the potential (H level) of the data line become the level of a threshold voltage Vth(n) of an N channel MOS transistor. Therefore, erroneous data will not be provided to the data line even in the case of insufficient equalization of an I/O line pair or when there is an offset in the differential amplifier circuit.

Amplifier circuit and complementary amplifier circuit with limiting

An improved output driver circuit for a semiconductor integrated circuit device, wherein a stepped control voltage generation circuit is connected to the gate of a driving transistor for driving an output terminal DQ. The stepped control voltage generation circuit responds to an applied input data signal to provide a stepped control voltage changing in a stepped form including a plurality of steps to the gate of the driving transistor. The driving transistor therefore changes its state on a step by step basis from a cut off state to a conduction state. Thus, sharp change in output current flowing through the output terminal can be prevented, and noise caused by a parasitic inductance can be avoided, thus preventing an erroneous operation in the device.

Output driver circuit for restraining generation of noise and

A substrate potential generating circuit can generate a lower substrate potential. The substrate potential generating circuit includes a clock signal generating circuit and first and second charge pump circuits. The first charge pump circuit including a p-channel MOS transistor having its source electrode connected to the semiconductor substrate applies a first negative potential to the drain electrode by capacitive coupling of a capacitor. The second charge pump circuit including first and second sub-charge pump circuit applies a third negative potential to the gate electrode when the first negative potential is applied to the drain electrode, and thereafter provides a second potential by lowering the third potential. As a result, the p-channel MOS transistor is turned on until a substrate potential is brought into a potential equal to the first potential applied to the drain electrode, lowering the substrate potential to the first potential.

Growing community of inventors

Hyogo, Japan

Yoshito Nakaoka