Fujitsu Corporation

Yoshito Koyama

Koji Nakamuta

Ken Atsumi

Yoshifumi Nakajima

Hideyuki Matsuura

Seiji Miyoshi

Minoru Hirahara

Yoshiharu Yoshizawa

Eiji Miyachika

Minoru Sakai

Masazumi Maeda

Yasutaka Kanayama

Koji Migita

Kazumasa Kubotera

A semiconductor device includes a delay part configured to assign a delay to an input signal, a phase detector configured to detect a phase of an output signal output from the delay part, a setting part configured to set a stable operations range of the phase of the output signal based on phase information output from the phase detector, and an error detector configured to set an acceptable range corresponding to the stable operations range, determine whether a phase of the output signal falls within the acceptable range, and change the acceptable range based on an extraneous factor of an input signal of the delay part.

Semiconductor device and information processing apparatus

A power supply device includes: a first supply section that supplies power in accordance with an extent of a load in processing in a processing device by applying a voltage to the processing device which processes data; and a second supply section that supplies, to the processing device, power smaller than the supplying power by the first supply section, in accordance with an extent of a load in processing in the processing device to increase and decrease a voltage with respect to the application voltage by the first supply section.

Method for suppressing a voltage fluctuation applying to a load by a second power section with the same or opposite voltage polarity

A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value.

PLL circuit, method of controlling PLL circuit, and digital circuit

An apparatus includes a voltage controlled oscillator for outputting a clock signal having an oscillation frequency in accordance with an input voltage; a convertor for converting the analog video signal inputted from the exterior into the digital video signal synchronizing with the clock signal outputted from the voltage controlled oscillator; a phase difference detector for detecting a phase difference between the composite synchronizing signal in the analog video signal and a feedback signal which corresponds to the clock signal from the voltage-controlled oscillator; and a voltage control unit for controlling the input voltage of the voltage controlled oscillator to change in response to the phase difference detected by the phase difference detector when the phase difference is within the certain range, and to maintain the input voltage intact when the phase difference is in exceed of the certain range.

Analog-digital converting apparatus and clock signal output apparatus

A digital PLL circuit includes: a digital phase comparator to detect a phase difference between a master clock and a slave clock and output a phase difference detection value; a correction circuit to correct the phase difference detection value to a phase value in accordance with a comparison result between the phase difference detection value and a threshold; and a slave clock generation circuit to generate the slave clock in accordance with the phase value.

Digital PLL circuit and clock generating method

A thermostatic-chamber temperature control device includes: a heating element for heating a thermostatic chamber; a bridge circuit having a temperature sensitive element whose resistance value varies in accordance with the temperature of the heating element; a detection circuit for detecting an unbalanced voltage of the bridge circuit; a PWM signal generating circuit for generating a PWM signal corresponding to the unbalanced voltage detected by the detection circuit; and a switching element that has a current output terminal connected to the heating element and a current input terminal connected to a power supply circuit and is driven on the basis of the PWM signal generated by the PWM signal generating circuit.

Temperature control device

A DLL circuit includes a delay line that adds, when receiving a reference signal, a delay amount to the phase of the reference signal by using each delay element and outputs a delay signal for each delay element. The DLL circuit includes a phase detector that compares the phase of a delay signal delayed by all the delay elements and the phase of the reference signal to obtain a phase difference by using the delay signal adjusted by a phase adjustment circuit and the reference signal. The DLL circuit includes a delay element control circuit that inputs a value, by which the delay signal to be compared by the phase detector is synchronized with the reference signal to be compared by the phase detector and which is a control voltage value generated from the phase difference output from the phase detector, into the delay elements of the delay line.

Phase control device, phase-control printed board, and control method

In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.

Phase controlling apparatus, phase-control printed board, and controlling method

A power supply voltage output circuit includes: a power supply voltage generation unit generating a power supply voltage to be supplied into a ring oscillator; a reference clock oscillator oscillating a reference clock with respect to a clock oscillated by the ring oscillator; a phase difference detection unit detecting a phase difference between the clock from the ring oscillator and the reference clock from the reference clock oscillator; a filter unit smoothing an output of the phase difference detection unit; and a PWM signal generation unit generating a PWM signal based on an output of the filter unit such that the phase difference approaches zero.

Power supply voltage output circuit

A power supply device of the invention includes: a supply section that supplies power to a second processing device which processes data in response to processing execution by a first processing device which processes data; a load detection section that detects a load of processing execution by the first processing device; and a power control section that causes the supply section to increase or decrease power supply according to the magnitude of load detected by the load detection section. The load of processing execution by the first processing device disposed in the upstream side relative to the second processing device is detected, and power supply to the second processing device is increased or decreased according to the detected magnitude of load. Accordingly, even when the amount of processing data sharply increases, sufficient power can be unfailingly supplied to the second processing device.

Power supply device having load detection function and communication apparatus provided with the power supply device

A DPLL circuit is provided for making it possible to inhibit an initial frequency offset during holdover. The DPLL circuit includes a slave oscillator for generating a frequency signal corresponding to the size of a control signal value; a phase difference detection circuit for detecting the difference in phase between the output of said slave oscillator and the inputted reference clock, and outputting a digital signal of the prescribed number of bits corresponding to said detected phase difference; and a holdover unit for generating a correction value based on the output of said phase difference detection circuit, wherein when the holdover is detected, said holdover unit periodically adds the correction value to the output of said phase difference detection circuit to obtain a control value for said slave oscillator.

Digital PLL circuit

To a frequency divider having a reset function, a second clock of a frequency N&#xd7;Y times higher than that of a first clock is inputted. Upon receipt of a signal indicating that the stop of the input clock is detected by a start/stop detection circuit, the frequency divider having a reset function resets the dividing of a frequency. Then, upon receipt of a signal indicating that the resumption of the input clock is detected by the start/stop detection circuit, the frequency divider generates and inputs a third clock to a phase comparator by starting the dividing of a frequency.

PLL circuit

Each clock supply unit comprises an inter-unit synchronization portion which operates when the clock supply unit is acting as a standby unit, using a clock signal from a DPLL of a unit which is active as reference, to apply a predetermined phase difference to the output clock signal of the DPLL of the unit to cause synchronization with the output clock signal of the DPLL of the active unit.

Clock supply device

The invention relates to a frequency synthesizer. An object of the invention is to provide a frequency synthesizer whose high stable performance is realized at an inexpensive cost. The frequency synthesizer includes a frequency synthesizing section generating an output signal by performing indirect frequency synthesis at a period which is equal to a product of a period of the reference signal and a first integer, and a clock generating section generating the clock signal by performing frequency synthesis for the output signal and for maintaining a frequency of the clock signal at a value which is equal to a difference between or a sum of a first frequency which is equal to a product of the frequency of the reference signal and a second integer and a second frequency indicating a number of times the phase difference is compressed.

Frequency synthesizer

In an atomic oscillator of an optical pumping system, a slot line resonator, as a microwave resonator, is arranged in a portion where atoms are excited. The slot line resonator forms a microstrip line inputting microwaves so as to be orthogonal to a slot line with a dielectric substrate being sandwiched therebetween. A container in which the atoms are enclosed is mounted on the slot line resonator, and the slot line resonator and the container are covered with a metallic case having a pumping light passage hole and a photo element.

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Kawasaki, Japan

Yoshito Koyama