Fujitsu Semiconductor Limited

Fujitsu Corporation

Yoshito Konno

Eiji Yoshida

Shigeyuki Maruyama

Yutaka Yamada

Naoyuki Watanabe

Toshimi Kawahara

Toshiyuki Honda

Kenichi Nagashige

Daisuke Koizumi

Naoya Sashida

Kazuo Teshirogi

Yuzo Shimobeppu

Tomoyuki Okada

Mitsuhisa Watanabe

Masahiko Minemura

Mitsufumi Naoe

Kanji Takeuchi

Shoko Saito

Yukihiro Sato

Yasuhiko Inada

Tomoaki Inaoka

Kyouhei Tamaki

A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.

Semiconductor wafer and method for manufacturing semiconductor device

A method of peeling an electronic component. The method includes a step of, when the electronic component is adhered onto a first main surface of a tape member, bringing a bellowphragm into contact with a second main surface, which is the other main surface of the tape member; and a step of, after the bellowphragm is brought into contact with the second main face, deforming the bellowphragm and the tape member by supplying a fluid to the bellowphragm to thereby peel the electronic component from the tape member.

Method and apparatus for peeling electronic component

A method for sorting and acquiring a semiconductor element, including: disposing a plurality of semiconductor elements in an effective section in a semiconductor substrate; disposing a standard semiconductor element outside of the effective section in the semiconductor substrate; forming a bump in each of the plurality of the semiconductor elements and in the standard semiconductor element; performing a test on the plurality of the semiconductor elements in the effective section; forming a location map using the standard semiconductor element as a base point; and picking up the semiconductor elements determined as non-defective in the test from the plurality of the semiconductor elements based on the location map.

Method for sorting and acquiring semiconductor element, method for producing semiconductor device, and semiconductor device

A method of manufacturing a semiconductor device, includes providing a mark above a main surface on a semiconductor substrate, separating the semiconductor substrate into a plurality of semiconductor elements by cutting the semiconductor substrate, determining a reference semiconductor element on the basis of a coordinate data indicating coordinates of the mark and coordinates of all of the semiconductor elements on the semiconductor substrate, and picking-out the semiconductor elements on the basis of the coordinate data using a pick-out apparatus. The providing operation includes forming a protective coat onto the main surface of the semiconductor substrate, irradiating a point on the main surface of the semiconductor substrate with a laser beam through the protective coat, and eliminating the protective coat from the main surface of the semiconductor substrate.

Method for fabricating semiconductor device

A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board. Displacements of the internal terminal resulting from the temperature load applied during testing of the wafer are compensated by the level transitioning portion of the first wiring. Unevenness involved with the contact between the contact electrodes on the probe card and the electrodes on the chips are compensated by the contact electrodes and/or elastic material. An electrode pitch of the contact electrodes is expanded by the first wiring.

Probe card and method of testing wafer having a plurality of semiconductor devices

A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board. Displacements of the internal terminal resulting from the temperature load applied during testing of the wafer are compensated by the level transitioning portion of the first wiring. Unevenness involved with the contact between the contact electrodes on the probe card and the electrodes on the chips are compensated by the contact electrodes and/or elastic material according to the present invention. An electrode pitch of the contact electrodes is expanded by the first wiring.

Semiconductor chips are formed on a wafer. The wafer is diced, while a dicing tape applied to the wafer is kept intact. Each of the semiconductor chips is fixed by suction and then removed from the dicing tape. Each of the semiconductor chips is unfixed by ceasing the suction and picked up and conveyed.

Semiconductor chip removing and conveying method and device

Growing community of inventors

Kawasaki, Japan

Yoshito Konno