Sony Corporation

Fujitsu Corporation

Yoshito Katano

Hideo Tanaka

Kazuhiro Sako

Sumie Aoki

Tadashi Yoshida

Kazuhiko; c/o Sony Lsi Design Inc Sako

Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section.

Bus system and deadlock avoidance circuit thereof

A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from the masters of the master group on the basis of the queue information and the bank information provided thereto and transmits the information to the memory controller as access control information.

Memory system, access control method therefor, and computer program

A flash memory is made to store a same boot program in a plurality of blocks in it. When a flash memory controller receives an access command for accessing the storage region storing the boot program from a CPU (Step S), it outputs the read out data to the CPU only when the corresponding block is not faulty according to the determination (Steps S, S) made on the basis of the ECC contained in the data read out from the corresponding page and the determination (Step S) made on the basis of the block information also contained in the data read out from the corresponding page. If, on the other hand it is determined that the block is faulty, the flash memory controller reads out the boot program stored in the next block (Steps S, S) and determines once again that the block is faulty or not faulty.

Semiconductor device and processing method for starting the same

When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit , is performed. As a result, a bit search process is quickly performed.

Bit search device and bit search method

When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a detecting circuit and a detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a detection process for detecting that bit data changes from to or a detection process for detecting that bit data changes from to is performed; and either a detection or a detection output operation, which is selected by a selector circuit is performed. As a result, a bit search process is quickly performed.

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Kanagawa, Japan

Yoshito Katano