Seiko Epson Corporation

Yoshiteru Ono

Hiroyasu Honda

Yukinari Shibata

Mihiro Nonoyama

Keitaro Fujimori

Yoshiro Iwasa

A flexible substrate including: a first part provided with a first device DV; a second part provided with a second device; a wiring part placed between the first part and the second part and including a plurality of wirings for coupling the first device and the second device; the first device including at least a first data transfer control unit, the second device including at least a second data transfer control unit, the first data transfer control unit and the second data transfer control unit transferring data by using a differential signal, and the plurality of wirings for coupling the first device and the second device including at least one differential signal line pair for transferring data by using a differential signal.

Flexible substrate and electronic equipment

A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slicehaving a plurality of basic cellsformed in a matrix, in which first and second power source wiringsandthat traverse the plurality of basic cellsare connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cellsand/or between the plurality of basic cells. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A-A, B-Band C-C; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list. The registered effective pin positions are provided on lattice gridslocated inside and outside a region between the first and second power source wiringsand. In the circuit wired according to the definitions, contacts with respect to the drains are provided inside and outside the region between the first and second power source wiringsand, and the signal wirings do not cross the power source wirings.

Master slice type semiconductor integrated circuit and method for designing the same

A semiconductor integrated circuit is provided in which the transistor size can be minimized by only changing one mask after the performance of a prototype is tested. Impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines and portions surrounded by broken lines) surrounded by a field insulating film on a semiconductor substrate for prototyping, and a prototype semiconductor integrated circuit is thereby manufactured, and then testing is performed. When the prototype semiconductor integrated circuit operates in a desired manner, impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines only) surrounded by a field insulating film on a semiconductor substrate for shipment, and a semiconductor integrated circuit for shipment is thereby manufactured.

Method for manufacturing semiconductor integrated circuit

A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice having a plurality of basic cells formed in a matrix, in which first and second power source wirings and that traverse the plurality of basic cells are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells and/or between the plurality of basic cells . The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list. The registered effective pin positions are provided on lattice grids , located inside and outside a region between the first and second power source wirings and . In the circuit wired according to the definitions, contacts with respect to the drains are provided inside and outside the region between the first and second power source wirings and , and the signal wirings do not cross the power source wirings.

Growing community of inventors

Suwa, Japan

Yoshiteru Ono