Fujitsu Corporation

Yoshiteru Ohnuki

Hideo Yamashita

Norihito Gomyo

Kouji Kimura

A semiconductor device includes an arithmetic circuit executing an arithmetic operation regarding input data, and a control circuit causing the arithmetic circuit to execute an arithmetic operation regarding first data that is an arithmetic operation target of an arithmetic command when the arithmetic command is included in a supplied command sequence, and causing the arithmetic circuit to execute an arithmetic operation regarding second data different from the first data when an arithmetic command is not included in the command sequence and the command sequence is in a specific state.

Semiconductor device and control method of semiconductor device

An arithmetic processing device includes: a first register configured to hold data to be used to execute an instruction; a second register configured to hold a portion of the data held in the first register; a computing circuit configured to execute computation using the data held in the second register; a first error detector configured to detect whether or not an error is included in the data to be transferred by the first register to the second register; a controller configured to interrupt the execution of the instruction if the first error detector detects the error in the data; and an error corrector configured to correct the error in the data held in the first register if the first error detector detects the error in the data.

Arithmetic processing device and method of controlling arithmetic processing device

A processor for processing data and correcting an error occurring in the data, the processor includes: a register that stores data with error check data and error correction data; an error detector that detects an error in the data stored in the register by using the error check data; and an error corrector that corrects the detected error by using the error correction data and that stores the corrected data back into the register.

Processor and error correcting method

A debugging mechanism receives arithmetic operation data inputs for causing an arithmetic unit to perform an arithmetic operation, and a control signal used for the arithmetic operation. The debugging mechanism includes a debug control unit which includes (1) a counter that performs a counting operation cyclically according to the processor clock operation, and (2) an OR circuit that receives the control signal and a counter signal that is output when the counter value becomes a specific value, and outputs an output signal generated by performing a logical OR operation of the control signal and the counter signal. The debugging mechanism also includes a debug storage unit which stores the arithmetic operation data, the counter value, and the control signal when the output of the OR circuit is valid.

Debugging mechanism having an OR circuit for triggering storage of arithmetic operation data whenever a valid control signal is received or a clock-based counter overflows

In an arithmetic processing unit adopting register windows, a configuration is made such that the reading process of a register file is controlled by two stages of a current window selection and a register selection, and the register selected at a plurality of reading ports of the register is set to each port in advance such that it will be out-of-order executable. Accordingly, the process of reading the data into an arithmetic section is possible without having a temporary memory, and an instruction subsequent to a window switching instruction is also out-of-order executable.

Register file having multiple windows and a current window pointer

A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.

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Kawasaki, Japan

Yoshiteru Ohnuki