Sharp Kabushiki Kaisha Corporation

Yoshiteru Ishimaru

Masafumi Shimizu

Yu Zhu

Naoki Takahashi

John Kevin Twynam

Motoko Furukawa

A bias circuitin a power amplifieris provided with a VBE-controlled voltage source circuitand a Nagata current mirror circuitThe Nagata current mirror circuitincludes a transistor Trand a transistor TrThe transistor Trhas its emitter grounded, its base connected to a control input terminalvia a resistor Rand its collector connected to that base via a resistor RThe transistor Trhas its emitter grounded, its base connected to the collector of the transistor Tr, and its collector connected to the base of the transistor TrThe arrangement is capable of compensating both the temperature characteristics of the gain of the power amplifierand the control input voltage characteristics of the gain of the power amplifierIn other words, the arrangement is capable of reducing the temperature dependence and control input voltage dependence of the gain of the power amplifier

Power amplifier and multistage amplification circuit including same

A heterojunction bipolar transistor has a stack comprised of a base layer, an emitter layer and a ballast layer made of AlGaAs. The emitter layer is comprised of a single layer or a multiplicity of layers, and at least one of which is comprised of a material that prevents hole injection from the base layer into the ballast layer. Thus, the hole injection from the base layer into the emitter layer is prevented. Accordingly, it is able to prevent the conductivity modulation of the ballast layer that is the cause of a deterioration in temperature characteristics.

Heterojunction bipolar transistor capable of restraining the conductivity modulation of the ballast layer

An emitter of a heterojunction bipolar transistor has a double-layer protrusion formed of a first emitter layer and a second emitter layer and protruded outside an external base region. The protrusion of 50 nm in total thickness is enough to prevent damage during formation of the protrusion by etching or during later fabricating processes. Penetration of moisture through damaged places is eliminated. A base ohmic electrode is continuously formed on the first and second emitter layers on the external base region up to the protrusion. Thus, the protrusion is reinforced so as to be further hard to damage. By ensuring a large area for the base ohmic electrode, an alignment margin can be taken during formation of a base lead electrode.

Heterojunction bipolar transistor, manufacturing method therefor, and communication device therewith

A method for analyzing a Schottky junction of the present invention includes the step of obtaining electrical field dependence of the Schottky barrier height which shows a degree of dependence of the Schottky barrier height of the Schottky junction formed on a semiconductor wafer on an electrical field applied to an interface of the Schottky junction in a case where a reverse bias is applied to the Schottky junction. The method includes the steps of: applying the reverse bias of a plurality of voltage values to the Schottky junction; measuring a plurality of current values of a current flowing through the Schottky junction and a plurality of capacitance values of the Schottky junction, corresponding to the reverse bias of the plurality of voltage values; obtaining current-voltage characteristics and capacitance-voltage characteristics of the Schottky junction based on the plurality of current values and the plurality of capacitance values; calculating depletion layer charge-voltage characteristics showing a correlation between an accumulated charge in a depletion layer and a voltage by integrating the capacitance-voltage characteristics with respect to a voltage; and obtaining the electrical field dependence of the Schottky barrier height based on the current-voltage characteristics and the depletion layer charge-voltage characteristics.

Method for analyzing schottky junction method for evaluating semiconductor wafer method for evaluating insulating film and schottky junction analyzing apparatus

A method for analyzing a Schottky junction includes the step of obtaining electrical field dependence of the Schottky barrier height which shows a degree of dependence of the Schottky barrier height of the Schottky junction formed on a semiconductor wafer on an electrical field applied to an interface of the Schottky junction in a case where a reverse bias is applied to the Schottky junction. The method includes the steps of: applying the reverse bias of a plurality of voltage values to the Schottky junction; measuring a plurality of current values of a current flowing through the Schottky junction and a plurality of capacitance values of the Schottky junction, corresponding to the reverse bias of the plurality of voltage values; obtaining current-voltage characteristics and capacitance-voltage characteristics of the Schottky junction based on the plurality of current values and the plurality of capacitance values; calculating depletion layer charge-voltage characteristics showing a correlation between an accumulated charge in a depletion layer and a voltage by integrating the capacitance-voltage characteristics with respect to a voltage; and obtaining the electrical field dependence of the Schottky barrier height based on the current-voltage characteristics and the depletion layer charge-voltage characteristics.

Method for analyzing Schottky junction, method for evaluating

A heterojunction semiconductor device includes a first Schottky contact layer made of a first semiconductor, a second Schottky contact layer made of a second semiconductor and a metal electrode. The first Schottky contact layer, the second Schottky contact layer and the metal electrode are laminated in this order on a semiconductor substrate or on a main structure of a semiconductor device laminated on a semiconductor substrate from the substrate side or from the main structure side. The first Schottky contact layer serves as a barrier layer toward the second Schottky contact layer, and a layer thickness of the second Schottky contact layer is greater than the mean free pass of carriers in the second Schottky contact layer.

Heterojunction semiconductor device

The method for fabricating a semiconductor device according to the present includes the steps of: forming an opening in an electron beam resist layer formed on a semiconductor substrate; forming an opening in a photoresist layer formed on the electron beam resist layer in such a manner that the opening formed at the electron beam layer is exposed, and that the opening formed in the photoresist layer has a larger dimension than that of the opening formed in the electron beam resist layer; and forming an electrode having a T-shaped cross section by depositing an electrode material via the two openings, wherein the electron beam resist layer is formed of a polymethacrylate type electron beam resist, and the photoresist layer is formed of a styrene resin type negative resist containing a phenolic hydroxyl group.

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Tenri, Japan

Yoshiteru Ishimaru