Hitachi, Ltd.

Hitachi Global Storage Technologies Netherlands B.v.

Yoshiteru Ishida

Terumi Takashi

Kazunori Iwabuchi

Akihiko Hirano

Hideyuki Yamakawa

Hiroshi Kimura

Kunio Watanabe

Naoki Satoh

Ryutaro Horita

Takashi Nara

Kenichi Hase

Atsushi Saito

Seiichi Mita

Hiromi Matsushige

Yoshiju Watanabe

Hitoshi Ogawa

Minoru Kosuge

Kazuhisa Shiraishi

Kazutoshi Ashikawa

In one embodiment, a write/read apparatus includes an external interface section for data input; an external interface section for data output; a memory for temporarily storing the data that is input through the external interface section for data input and written on the recording medium and the data that is read from the recording medium and sent to the outside through the external interface section for data output; an address generating section for generating unique addresses associated with physical block addresses of the recording medium; a flag generating section for generating flags for prohibiting overwriting of the data to be written on the recording medium; and a processing section for adding the unique addresses generated in the address generating section to the data that is stored in the memory and that is to be written on the recording medium. The data with the addition of the flags generated in the flag generating section and the unique addresses is written on the recording medium.

Write/read apparatus to control overwriting

Embodiments of the invention increase the convenience of a magnetic disk drive for portable use by shortening a period of time required to record a large amount of data, and by increasing the reproduction time, in the magnetic disk drive. In one embodiment, an area between servo data parts is interpolated by servo data parts, each of which stores a burst signal, so that the allocation density of a burst signal is made k times. At the time of write operation in which data is written, only the servo data parts are made use of to perform the servo control while a disk is driven at high rotational speed so as to reduce the recording time. At the time of read operation in which data is reproduced, the servo data parts are made use of to ensure the required precision of the servo control at low rotational speed that is 1/k of the rotational speed at the time of write operation. The reproduction at low rotational speed enables the reduction in power consumption.

Magnetic disk drive and magnetic disk medium

A reproduced signal processing circuit includes a variable gain amplifier to which a signal read from a medium by a reproducing head is inputted; an analog-to-digital converter for converting a signal outputted from the variable gain amplifier into a digital signal; and a variable frequency oscillator for supplying an operation clock signal to the analog-to-digital converter. A reproduced signal processing method includes the steps of operating a first control loop for controlling the variable gain amplifier; operating at least either one of a second control loop and a third control loop, the second control loop controlling the variable frequency oscillator, the third control loop controlling the variable frequency oscillator; filtering by analog filter means the read signal inputted to the variable gain amplifier; operating at least one of first, second, and third noise detecting operations, the first noise detecting operation detecting presence or absence of a noise by comparing an amplitude of the output signal from the variable gain amplifier with a predetermined threshold value, the second noise detecting operation detecting a noise during an operation period of the second control loop, the third noise detecting operation detecting a noise during an operation period of the third control loop; and changing the range of cutoff frequency of the analog filter means in accordance with a result from at least one of the first, second, and third noise detecting operations, thereby controlling at least one of the first, second, and third control loops.

Reproduced signal processing method, reproduced signal processing

A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.

Signal processing delay circuit

A data discrimination apparatus which is capable of correcting a decrease in amplitude of a signal to be data discriminated by a correction value so as to correct the bit itself which was used as a target bit to determine the correction value. A decision circuit preliminarily classifies an equalizer output into symbols '0' and '1' to obtain a run length of the symbol '0' with respect to a given symbol '1' (the target bit). A correction value generating circuit includes a memory device which contains correction values in correspondence with all the possible values of the run length, and outputs one of the correction values out of the memory device in response to an output from the decision circuit. A delay circuit delays the equalizer output by a time which is required until the correction value is output. An operation circuit adds the selected correction value to the delayed equalizer output, to correct the same. The thus corrected equalizer output is data discriminated in a data discrimination circuit, with a lowered error rate owing to the correction.

Magnetic disk drive including a data discrimination apparatus capable of

A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.

Information recording/reproducing apparatus having a clock timing

An AGC circuit is provided with a variable gain amplifier which changes an amplification gain of an input signal in accordance with an instruction; an extraction unit for extracting a value of an output of the variable gain amplifier at a predetermined interval; and a variable gain control unit for instructing the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the value extracted by the extraction unit. The variable gain control unit is provided with an error signal output device for squaring the value extracted by the extraction unit and for generating an error signal to instruct the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the square value and a square value just before it; and an integrating device for integrating the error signal from the error signal output device and for instructing the amplification gain of the variable gain amplifier.

AGC circuit and recording and reproducing apparatus using AGC circuit

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Odawara, Japan

Yoshiteru Ishida