Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Yoshiteru Hayashi

Hiroshi Amano

Takeshi Tanaka

Takashi Hashimoto

Masayasu Iguchi

Satoshi Kajita

A processor performs, in accordance with a single instruction, multiplication processing and comparison processing. The multiplication processing includes obtaining a multiplication result by multiplying together a first data element and a first value. The comparison processing includes comparing the multiplication result with a second data element. The first data element is stored in a first register, the second data element is stored in a second register, and the first value is stored in a third register.

Processor and method for controlling the processor

An image decoding device is provided that decodes, without an increase in the circuit size, a coded video sequence including a large-size block. The image decoding apparatus includes: a block division unit which divides a current block that is to be decoded and is included in a picture of the coded video sequence, into sub-blocks; an image obtainment unit which obtains, for each of the sub-blocks, image data corresponding to the sub-block from a recording medium; a prediction unit which generates, for each of the sub-blocks, a predicted image of the sub-block, based on the image data obtained by the image obtainment unit; and a reconstruction unit which reconstructs each of the sub-blocks, by adding the predicted image generated for the sub-block to the sub-block.

Image decoding apparatus, image decoding method, integrated circuit, and program

A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit () which decodes, from a coded stream, a plurality of motion compensation filter coefficients; a memory () for holding the motion compensation filter coefficients included in the coded stream; a filter coefficient storage unit () for holding at least one of the motion compensation filter coefficients which is required for the motion compensation; a motion compensation unit () which performs motion compensation using the required motion compensation filter coefficient held in the filter coefficient storage unit; and a filter coefficient transfer control unit () which writes, in the memory, the motion compensation filter coefficients decoded by the decoding unit, and transfers the required motion compensation filter coefficient from the memory to the filter coefficient storage unit, only when the required coefficient is not yet stored therein.

Moving image decoding apparatus, moving image coding apparatus, moving image decoding circuit, and moving image decoding method

An image decoding apparatus which decodes, in parallel, a coded stream having processing order dependency includes: a slice data predecoding unit which predecodes, on a macroblock group basis, macroblock groups included in the coded stream to generate macroblock decoding information necessary for decoding other macroblock groups; and a first macroblock decoding unit and a second macroblock decoding unit each of which decodes a corresponding one of macroblock groups included in the coded stream in parallel. Each of the macroblock decoding units, when decoding the corresponding one of macroblock groups, uses the macroblock decoding information that has been generated for the other macroblock group.

Image decoding apparatus and image coding apparatus wth parallel decoding

A symmetric filter arithmetic apparatus includes a first data shuffling unit which reads a first data string that is a plurality of consecutive pieces of data from a register file and extract, from the first data string, a left-side data string that is a plurality of consecutive pieces of data to be multiplied by a left-side filter coefficient that is a filter coefficient on a left side of a center of the coefficients, and a second data shuffling unit which reads a second data string that is a plurality of consecutive pieces of data from the register file and extract, from the second data string, a right-side data string that is a plurality of consecutive pieces of data to be multiplied by a right-side filter coefficient that is a filter coefficient on a right side of the center and is the same value as the left-side filter coefficient.

Symmetric filter arithmetic apparatus and symmetric filter arithmetic method

A decoding apparatus according to the present invention includes: a decoding unit which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit to the orthogonal transfer basis storage unit only when the identified orthogonal transform basis is not yet stored therein. With this structure, it is possible to reduce the memory bandwidth for the memory storing the orthogonal transform basis and the memory access latency.

Image decoding apparatus, image coding apparatus, image decoding circuit, and image decoding method

An image decoding device capable of performing parallel decoding of coded image data with a small memory bandwidth while suppressing momentary increase in the amount of data transferred for the decoding. An image decoding device () includes: an external memory () which stores data of reference images; a stream parser unit () which decodes reference information indicating the number of reference images to be referred to on a block-by-block basis; an amount-of-transferred-data prediction unit () which calculates, on a block-by-block basis using the reference information, a predictive data amount of a reference image to be read out from the external memory (); a block determination unit () which determines, using the predictive data amount, multiple blocks to be decoded in parallel, so as to reduce variation in amounts of data read out from the external memory (); and macroblock decoding units (to) which decode the determined blocks in parallel.

Image decoding device, image decoding method, integrated circuit, and program for performing parallel decoding of coded image data

A decoding apparatus () according to the present invention includes: a decoding unit () which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit () accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit () storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit () which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit () which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit () to the orthogonal transfer basis storage unit () only when the identified orthogonal transform basis is not yet stored therein. With this structure, it is possible to reduce the memory bandwidth for the memory storing the orthogonal transform basis and the memory access latency.

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Kyoto, Japan

Yoshiteru Hayashi