Renesas Electronics Corporation

Yoshitaka Taki

Tadaaki Tanimoto

Tatsuya Kamei

Yoichi Yuyama

Yoichi Maeda

Daisuke Moriyama

Akihiro Yamate

Susumu Abe

Shunsuke Nakano

In a semiconductor device including a lockstep function, conflicts of bus accesses by a plurality of processors are suppressed. The semiconductor device includes a first processor, a second processor for monitoring operation of the first processor in a first mode, first and second buses, first and second non-shared resources dedicated to either the first or second processor in a second mode, and a first selector for selecting a bus for transferring interface signals between the second processor and the selected bus. In a second mode in which the first and second processors execute different instructions, the first selector selects the second bus. In the second mode, the first non-shared resource is accessed by the first processor via the first bus and the second non-shared resource is accessed by the second processor via the second bus.

Semiconductor device and method of operating the same

Provided is a semiconductor device which can perform secure data transmission/reception considering functional safety. The semiconductor device includes a hardware security module circuit which performs an authentication process and an error detection circuit used to perform an error detection process at least on first data which is processed in the hardware security module circuit. A memory area associated with the error detection circuit is configured to be accessible only by the hardware security module circuit when the error detection process is performed at least on the first data.

Semiconductor device, authentication system, and authentication method

Existing semiconductor devices cannot detect a failure occurring in a circuit required for mode switching processing for other than arithmetic cores, so that reliability is inadequate. A semiconductor device of an embodiment of the invention includes: a selector which is provided corresponding to among plural arithmetic cores one used as a checking arithmetic core in lock-step mode and which, in lock-step mode, blocks the interface signals outputted from the corresponding arithmetic core and, in split mode, lets the interface signals outputted from the corresponding arithmetic core through; an access monitor which monitors the interface signals outputted via a selector and, when an abnormal state of the interface signals is detected, outputs an error signal; and an error control unit which outputs, based on the error signal outputted from the access monitor, an abnormal state processing request to a higher-order system.

Semiconductor device and failure detection system

A semiconductor device () includes a first processing unit (-), a second processing unit (-), a writing unit (), a storage unit (), and a processing control unit (). The writing unit () writes first information related to processing of each of the first processing unit (-) and the second processing unit (-) into the storage unit (). The processing control unit () controls the operations of the first processing unit (-) and the second processing unit (-). The processing control unit () performs control to stop the first processing unit (-) when an error occurs in the first processing unit (-). When it is determined that the second processing unit (-) where an error has not occurred is able to maintain execution of the first processing by using first information stored in the storage unit (), the second processing unit (-) maintains execution of the first processing.

Semiconductor device and control method thereof including a plurality of processing units

A semiconductor device includes a first circuit and a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit. A pattern-generator control circuit controls each of the plurality of pattern generators such that the pattern generator starts to operate when a control signal is at a first level and the pattern generator stops operating when the control signal is not at the first level. A pattern compressor compresses a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators. A pattern-compressor control circuit controls the pattern compressor. A self-diagnosis control circuit is connected to the pattern-generator control circuit and the pattern-compressor control circuit and controls the pattern-generator control circuit such that stop timings of the test patterns differ from one another among the plurality of pattern generators due to changing the control signals to selectively stop the pattern generators in a predetermined manner.

Semiconductor device

An SSCG generating a center-spread modulated clock centering on a frequency obtained by multiplying an input reference clock frequency by a predetermined number is configured to include a phase comparator, a VCO, and a modulation circuit formed by a frequency divider and a division ratio modulation circuit. The division ratio modulation circuit supplies the frequency divider with a division ratio modulated above and below the predetermined multiplication number, and outputs a magnitude relationship involved as a spread direction identification signal. The diagnostic circuit includes a counter that counts the modulated clock and, based on the spread direction identification signal, performs counting operations during an up-spread or down-spread period. Based on the values counted for a predetermined period, the operating status of the SSCG is diagnosed for the presence or absence of a failure, for example.

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Tokyo, Japan

Yoshitaka Taki