Hitachi, Ltd.

Texas Instruments Corporation

Olympus Corporation

Other

Hiatchi, Ltd.

Texas Instruments Japan Limited

Yoshitaka Tadaki

Toshihiro Sekiguchi

Jun Murata

Keizo Kawakita

Isamu Asano

Hideo Aoki

Songsu Cho

Michio Nishimura

Katsuo Yuhara

Hiroko Kaneko

Michio Tanaka

Toshiyuki Kaeriyama

Kazuhiko Saitoh

Hiroyuki Uchiyama

Yuji Ezaki

Masakazu Sagawa

Atsushi Hiraiwa

Shinji Shimizu

Mitsuaki Horiuchi

Jun Sugiura

Hidetsugu Ogishi

Masami Ozawa

Norio Hasegawa

Makoto Yoshida

Shuntaro Machida

Hiroyuki Enomoto

Takahiro Kumauchi

Shinya Nishio

Satoru Yamada

Yoshitaka Nakamura

Tsuyoshi Tamaru

Takuya Fukuda

Osamu Kasahara

Masayoshi Hirasawa

Toshikazu Kumai

Yutaka Kobayashi

Masayuki Suzuki

Masayuki Kojima

Hisashi Nakamura

Kazuo Nojiri

Atsuyoshi Koike

Hiromichi Enami

Hiroyuki Miyazawa

Atsushi Ogishima

Masayoshi Saito

Haruhisa Saito

Naoki Fukuda

Hidekazu Goto

Hisao Asakura

Yoshiaki Takemoto

Michimasa Funabashi

Toshio Maeda

Masaki Nagao

Naohiro Takazawa

Yasuo Kiguchi

Kazuya Kadota

Minoru Ohtsuka

Tadashi Chikahara

Masato Sadaoka

Kazuhiko Saito

Kazuhiko Kajigaya

Masashi Horiguchi

Hiroshi Kikuchi

Takeshi Sakai

Makoto Ohkura

Aritoshi Sugimoto

Tatsuya Nagata

Ryo Nagai

Yuichi Gomi

Masayuki Nakamura

Shinichi Fukada

Makoto Ogasawara

Kiyonori Ohyu

Mitsuhiro Tsukimura

Masafumi Miyamoto

Masayuki Yasuda

Takatoshi Kakizaki

Takashi Hayakawa

Yutaka Ito

Masakazu Aoki

Toshiyuki Mine

Hiromasa Noda

Katsuhiro Shimohigashi

Naoki Yamamoto

Shinichi Miyatake

Osamu Tsuchiya

Katsuyuki Sato

Hidetoshi Iwai

Takafumi Tokunaga

Yuzuru Ohji

Youji Idei

Kiyomi Katsuyama

Makoto Saeki

Hiroshige Kogayu

Chihiro Migita

Akihiko Konno

Tsuyuki Suzuki

Kunihiro Yagi

Masahiro Hyoma

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.

Semiconductor device

A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.

Solid-state imaging device, imaging apparatus, substrate, semiconductor device and method of manufacturing the solid-state imaging device

A wiring substrate may include: a base having a predetermined thickness; a plurality of electrode portions formed to protrude on one surface in a thickness direction of the base; a wiring provided in the base and electrically connected to the electrode portions; and a resin layer formed on the base to fill between the plurality of electrode portions. An upper surface of the resin layer may be formed in a concave shape lower than a maximum height of the electrode portion, and an upper surface of the electrode portion and the upper surface of the resin layer form a continuous curved surface.

Wiring substrate having conductive bumps with resin sealing between bumps and method of making

A semiconductor wafer may include: a disk-shaped wafer body made of silicon; and an identification trench section having at least one trench and provided at a periphery section of the wafer body, wherein the trench is opened in the periphery of the wafer body, and has a depth less than a thickness of the wafer body.

Semiconductor wafer and semiconductor device

An ultrasonic transducer includes a first electrode, a first insulation film covering the first electrode, a hollow part overlapping the first electrode on the first insulation film, a second insulation film covering the hollow part, a second electrode overlapping the hollow part on the second insulation film, and an interconnection joined to the second electrode. An edge of the first electrode is formed so as to moderate a step of the first electrode.

Ultrasonic transducer and manufacturing method

This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.

An ultrasonic transducer includes a first electrode, a second electrode, an insulating film disposed between the first and second electrodes, and a cavity disposed between the first and second electrodes. The insulating film includes a projection extending in the cavity, and a portion of the cavity is disposed between the projection and the first electrode. A portion of one of the first electrode and the second electrode has an opening corresponding to a position of the projection of the insulating film when viewed in plan view.

Ultrasonic transducer and manufacturing method thereof

Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.

This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, &#x2014;an insulation film covering the lower electrodes, &#x2014;plural hollow parts formed to overlap the lower electrodes on the insulation film, &#x2014;an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, &#x2014;the surfaces of the hollow parts and insulation film are flattened to the same height.

In a dual polymetal gate electrode, the contact resistance at the interface of silicon films increases due to mutual-diffusion of impurities of p-type and n-type silicon films through a refractory metal and metal nitride deposited thereon. A way of inhibiting the phenomenon is carbon implantation into a refractory metal and refractory metal nitride on the boundary of p-type silicon and n-type silicon, cutting the path, or isolating it by an insulator. Thereby, mutual-diffusion of impurities through a refractory metallic film and nitride film of refractory metal is inhibited, resulting in an increase in the contact resistance of metal nitride film and silicon film and a decrease in the deviation of threshold voltage of the MISFET.

Semiconductor integrated circuit device and manufacturing method thereof

An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (). The memory-cell selection MISFET (Qs) has an insulated gate electrode () (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate () with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode () (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate () with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices

In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500&deg; C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500&deg; C. or lower at a step after the MISFET has been formed.

Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines

Growing community of inventors

Hanno, Japan

Yoshitaka Tadaki