Kawasaki Microelectronics, Inc.

Ablic Inc.

Sii Semiconductor Corporation

Seikoh Giken Co., Ltd.

Yoshitaka Kimura

Masaru Akino

Yukihiro Imura

Kunio Yamada

Takehiko Narita

Satoshi Suzuki

Yuichi Arai

A semiconductor device includes a lead frame having a die pad; a semiconductor chip having a front surface in which an integrated circuit is formed, and a back surface that is die-bonded onto the die pad through intermediation of an interposing film and an adhesive layer; and an encapsulating resin for encapsulating the lead frame, the adhesive layer, the interposing film, and the semiconductor chip. The interposing film has a first opening which forms a space between a part of the back surface of the semiconductor chip and the adhesive layer.

Semiconductor device

A semiconductor device includes a multilayer wiring structure on a substrate. The multilayer wiring structure includes: a top wiring; a fuse element, which is located on a lower layer-side of the top wiring, and is made of metal having a melting point that is higher than that of the top wiring; and a lower-layer wiring, which is connected to each of ends of the fuse element. Provided is a semiconductor device in which fuse elements made of the high-melting point metal are arranged at high density.

Provided is a semiconductor device preventing readhesion of conductive body which forms fuse elements and breakage of the fuse elements. The semiconductor device includes a first insulating film formed on a semiconductor substrate, a plurality of fuse elements formed on the first insulating film adjacent to one another, a protective insulating film covering at least side surfaces of the fuse elements, and a second insulating film formed of one of a BPSG film and a PSG film to cover the fuse elements and the protective insulating film. The protective insulating film is higher in mechanical strength than the second insulating film.

Semiconductor device having fuse elements

A corrosion-resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. An array of intersecting metal lines forming windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. A silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent entry of moisture.

Semiconductor device having fuse element

A corrosion resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. A metal lattice having a plurality of windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. Alternatively, a metal array having a plurality of independent light-shielding portions may be disposed over the fuse elements to prevent the laser light from adversely affecting circuitry on the front surface side of the semiconductor device.

Semiconductor device having a fuse element

An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit region includes a plurality of circuit patterns, which form circuit elements of the semiconductor integrated circuit, in a plurality of pattern layers. The dummy region includes a plurality of character dummies, which do not contribute to an operation of the semiconductor integrated circuit. The character dummies have a fixed shape and dimension, and arranged in a character pattern layer selected from the plurality of pattern layers with a fixed pitch. The dummy region further includes an identification sign formed by connecting selected ones of the character dummies chosen from the plurality of the character dummies.

Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof

A semiconductor integrated circuit having a multilayer wiring structure is provided which includes: a top metal wiring layer (M) including a plurality of top layer power supply wirings and a next-to-top metal wiring layer (M) directly below the top metal wiring layer Mincluding a plurality of next-to-top layer power supply wirings. Each of the top layer and the next-to-top layer power supply wirings also includes first potential wirings for supplying a first potential to the circuit elements and second potential wirings for supplying a second potential to the circuit elements. The top layer power supply wirings and the next-to-top layer power supply wirings cross each other and have a top layer insulating film disposed between them. First and second contacts are provided in the insulating film for connecting the first potential wirings and second potential wirings in the top and the next-to-top metal wiring layers with each other.

Semiconductor integrated circuit

A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile data is stored by flowing a drain current in one of a pair of pull-down transistors constituting the SRAM cell while supplying a fixed potential to the sources of the pull-down transistors. A semiconductor integrated circuit including a SRAM block and a control circuit that controls the SRAM block to store non-volatile data is also disclosed.

Method of operating semiconductor integrated circuit including SRAM block and semiconductor integrated circuit including SRAM block

A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.

Silicon on insulator device and layout method of the same

The center of a turntable moves around the central axial line of an autoroation disk along the circular orbit C of a smaller diameter than that of an autorotation disk . Thus, the turntable revolves both around a center point O and on its own axis in accordance with an autorotation of the autorotation disk . A polishing holder holds a connector of an optical fiber polished by a polishing film arranged on the upper plane of the turntable . An optical fiber end face polishing machine provided with a memory for storing a control program which allows a control device to execute predetermined polishing steps, the control device being for controlling an autorotation motor of the turntable and a revolution motor thereof.

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Chiba, Japan

Yoshitaka Kimura