Dowa Electronics Materials Co., Ltd.

Wavesquare Inc.

Bbsa Limited

Dowa Holdings Co., Ltd.

Yoshitaka Kadowaki

Ryuichi Toba

Seog Woo Lee

Meoung Whan Cho

Tatsunori Toyota

Pil Guk Jang

Osamu Tanaka

Yuta Koshika

Tetsuya Ikuta

Masahito Miyashita

Shogo Sakuraba

Provided is a method of producing a semiconductor optical device that makes it possible to improve the optical device properties of the semiconductor optical device including semiconductor layers containing at least In, As, and Sb. The method has a first step of forming an etching stop layer on an InAs growth substrate; a second step of forming a semiconductor laminate; a third step of forming a distribution portion; a fourth step of bonding the semiconductor laminate and the distribution portion to a support substrate with a metal bonding layer therebetween; and a fifth step of removing the InAs growth substrate.

Semiconductor optical device and method of producing the same

In a light-emitting element including a first InAs layer that is undoped or doped with an n-type dopant; an active layer including one or more InAsSblayers (0<y<1); and a second InAs layer doped with a p-type dopant, an AlInAs electron blocking layer (0.05≤x≤0.40) with a thickness of 5 nm to 40 nm is provided between the active layer and the second InAs layer.

Light-emitting element and method of producing the same

Provided is a semiconductor light-emitting element that exhibits a light emission spectrum in which a single peak is obtained by controlling multi peaks. In the semiconductor light-emitting element having a second conductivity type cladding layer on the light extraction side, the arithmetic mean roughness Ra of a surface of the light extraction surface of the second conductivity type cladding layer is 0.07 μm or more and 0.7 μm or less, and the skewness Rsk of the surface is a positive value.

Semiconductor light-emitting element and method of producing the same

A method of manufacturing a semiconductor optical device of this disclosure includes the steps of forming an etch stop layer on an InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and forming a semiconductor laminate on the etch stop layer by stacking a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P. Further, an intermediate article of a semiconductor optical device of the present disclosure includes an InP growth substrate; an etch stop layer formed on the InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and a semiconductor laminate formed on the etch stop layer, including a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P stacked one another.

Method of manufacturing semiconductor optical device and intermediate article of semiconductor optical device

Provided is a semiconductor light-emitting element having improved light emission output. The semiconductor light-emitting element includes a light-emitting layer having a layered structure in which a first III-V compound semiconductor layer and a second III-V compound semiconductor layer having different composition ratios are repeatedly stacked. The first and second III-V compound semiconductor layers each contain three or more types of elements that are selected from Al, Ga, and In and from As, Sb, and P. The composition wavelength difference between the composition wavelength of the first III-V compound semiconductor layer and the composition wavelength of the second III-V compound semiconductor layer is 50 nm or less. The ratio of the lattice constant difference between the lattice constant of the first III-V compound semiconductor layer and the lattice constant of the second III-V compound semiconductor layer is not less than 0.05% and not more than 0.60%.

Semiconductor light-emitting element and method of producing semiconductor light-emitting element

Provided is a high quality III nitride semiconductor device in which, not only X-shaped cracks extending from the vicinity of the corners of semiconductor structures to the center portion thereof, but also crack spots at the center portion can be prevented from being formed and can provide a method of efficiently manufacturing the III nitride semiconductor device. The III nitride semiconductor device of the present invention includes a support and two semiconductor structures having a nearly quadrangular transverse cross-sectional shape that are provided on the support. The two semiconductor structures are situated such that one side surface of one of the two semiconductor structures is placed to face one side surface of the other of them. The support covers the other three side surfaces and of the four sides of the semiconductor structures.

III nitride semiconductor device and method of manufacturing the same

When an uneven pattern is formed on a light extraction surface composed of a semiconductor crystal by wet-etching using an alkaline solution, a plurality of convex portions cannot be formed in a desired arrangement. A method of manufacturing a semiconductor light emitting device includes a light extraction surface composed of a semiconductor crystal, wherein when the uneven pattern is formed by a plurality of convex portions on the light extraction surface, first, a plurality of impressions are formed on the light extraction surface of a semiconductor layer composed of a semiconductor crystal using a processing substrate, and next, by applying wet-etching to the light extraction surface using an alkaline solution, to thereby form convex portions with a portion where each impression is formed as a top portion, and a plurality of facets of the semiconductor crystal as a side face thereof.

Method of manufacturing semiconductor light emitting device, and semiconductor light emitting device

A method for manufacturing a vertically structured Group III nitride semiconductor LED chip includes a first step of forming a light emitting structure laminate; a second step of forming a plurality of separate light emitting structures by partially removing the light emitting structure laminate to partially expose the growth substrate; a third step of forming a conductive support, which conductive support integrally supporting the light emitting structures; a fourth step of separating the growth substrate by removing the lift-off layer; and a fifth step of dividing the conductive support between the light emitting structures thereby singulating a plurality of LED chips each having the light emitting structure. A first through-hole is formed to open in a central region of each of the light emitting structures such that at least the lift-off layer is exposed, and an etchant is supplied from the first through-hole in the fourth step.

Vertically structured group III nitride semiconductor LED chip and method for manufacturing the same

A luminescent device and a manufacturing method for the luminescent device and a semiconductor device which are free from occurrence of cracks in a compound semiconductor layer due to the internal stress in the compound semiconductor layer at the time of chemical lift-off. The luminescent device manufacturing method includes forming a device region on part of an epitaxial substrate through a lift-off layer; forming a sacrificing portion, being not removed in a chemical lift-off step, around device region on epitaxial substrate; covering epitaxial substrate and semiconductor layer and forming a covering layer such that level of surface thereof in the region away from device region is lower than luminescent layer surface; removing covering layer on semiconductor layer, and that on sacrificing portion surface; forming a reflection layer on covering layer surface and semiconductor layer surface; and forming a supporting substrate by providing plating on reflection layer.

Luminescent device and manufacturing method for luminescent device and semiconductor device

Provided are a III nitride semiconductor device which can be operated at a lower voltage can be provided, in which device a good ohmic contact is achieved between the (000-1) plane side of the III nitride semiconductor layer and the electrode and a method of producing the III nitride semiconductor device. A III nitride semiconductor device of the present invention includes a plurality of protrusions rounded like domes in a predetermined region on the (000-1) plane side of the III nitride semiconductor layer; and an electrode on the upper surface of the predetermined region.

III nitride semiconductor device and method of producing the same

The method of manufacturing a semiconductor device according to the present invention includes: a step of forming a semiconductor laminate on a growth substrate with a lift-off layer therebetween; a step of providing grooves in a grid pattern in the semiconductor laminate, thereby forming a plurality of semiconductor structures each having a nearly quadrangular transverse cross-sectional shape; a step of forming a conductive support body; and a step of removing the lift-off layer using a chemical lift-off process, in which step, in supplying an etchant to the grooves via through-holes provided in a portion above the grooves, the lift-off layer is etched from only one side surface of each semiconductor structure.

Semiconductor device and method of manufacturing the same

A method for manufacturing vertically structured Group III nitride semiconductor LED chips includes a step of forming a light emitting laminate on a growth substrate; a step of forming a plurality of separate light emitting structures by partially removing the light emitting laminate to partially expose the growth substrate; a step of forming a conductive support on the plurality of light emitting structures; a step of lifting off the growth substrate from the plurality of light emitting structures; and a step of cutting the conductive support thereby singulating a plurality of LED chips each having the light emitting structure. The step of partially removing the light emitting laminate is performed such that each of the plurality of light emitting structures has a top view shape of a circle or a 4n-gon ('n' is a positive integer) having rounded corners.

The purpose of the present invention is to provide a good ohmic contact for an n-type Group-III nitride semiconductor. An n-type GaN layer and a p-type GaN layer are aequentially formed on a lift-off layer (growth step). A p-side electrode is formed on the top face of the p-type GaN layer. A copper block is formed over the entire area of the top face through a cap metal. Then, the lift-off layer is removed by making a chemical treatment (lift-off step). Then, a laminate structure constituted by the n-type GaN layer, with which the surface of the N polar plane has been exposed, and the p-type GaN layer is subjected to anisotropic wet etching (surface etching step). The N-polar surface after the etching has irregularities constituted by {10-1-1} planes. Then, an n-side electrode is formed on the bottom face of the n-type GaN layer (electrode formation step).

Growing community of inventors

Tokyo, Japan

Yoshitaka Kadowaki