Nec Corporation

Nec Electronics Corporation

Yoshitaka Izawa

Yoshikazu Yabe

Toru Awashima

A delay library generation apparatus, associated control method, and associated program are provided. The delay library generation apparatus comprises a storage device which stores architecture information of a logic element array, layout data of an overall programmable logic device, a netlist of the overall programmable logic device, and a wiring route extraction unit which refers to the storage device and extracts wiring route information regarding a wiring route section based on the architecture information. Moreover, the delay library generation apparatus comprises an analyzing unit which analyzes the layout data of the logic device and extracts parameters of a parasitic element and a crosstalk between adjacent interconnections. The delay generation apparatus further comprises a delay calculation unit which calculates delay data based on the extracted parameters and a delay library generation unit which generates a delay library of the logic device based on the wiring route information and the delay data.

Delay library generation apparatus and method based on wiring arrangements

Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memorythat stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuitthat adjusts the timing of a layout information indicating signal Pin outputted from the layout information memoryat every clock cycle, and a wiring connection circuitthat changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unitand an arithmetic logic unit) based on a layout information indicating signal Pout whose timing has been adjusted.

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Kanagawa, Japan

Yoshitaka Izawa