Renesas Electronics Corporation

Honda Motor Co., Ltd.

Nec Electronics Corporation

Yoshitaka Hirai

Nobuharu Nagaoka

Akira Sakamoto

Takayuki Ogawa

Masahito Watanabe

Masakazu Saka

Tatsuya Sakai

Atsushi Motozawa

Hirotaka Itoh

Masahide Ueda

Manato Saitou

Minoru Tsuchida

Toshiya Okabe

Hirotsune Fukei

An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional pathis provided in a first power supply systemand outputs analog proportional signal AP according to a detection signal DET. An integral pathis provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driveris provided in the first power supply systemand outputs control current ICCO according to the AP and the AI. A CCOis provided in the second power supply systemand outputs an output signal Fout according to the ICCO. A phase frequency detectoris provided in the second power supply systemand configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.

Semiconductor device and PLL circuit

An optical axis angle inspection device is provided with a first camera and a screen which are disposed in front of a laser distance meter, is provided with a point light source on the screen, and is provided with a second camera disposed behind the laser distance meter. An image of the laser distance meter is captured by the first camera, and the height of the point light source is fitted to the height of the laser distance meter on the basis of the captured image. Then, an image of the point light source is captured by the second camera, and a difference in height between the centroid of the captured image and the point light source is specified. The optical axis angle of the laser distance meter is calculated from the difference in height and the distance from the screen to the laser distance meter.

Optical axis angle inspection device

According to one embodiment, a PLL circuit includes: a phase comparator (); a pulse width control unit that adjusts a pulse width of comparison results (UP, DN) of the phase comparator () and outputs comparison results (UPi, DNi) having a pulse width smaller than that of comparison results (UPp, DNp); a charge pump () that outputs a current (Ip) according to the comparison results (UPp, DNp); a charge pump () that outputs a current (Ii) according to the comparison results (UPi, DNi); a filter () that removes a high-frequency component of a voltage generated based on the current (Ip) and outputs a control voltage (Vp); a filter () that outputs, as a control voltage (Vi), a result obtained by integrating the current (Ii); and a voltage control oscillator () that generates an oscillating signal having a frequency according to the control voltage (Vp, Vi).

PLL circuit and control method thereof

An inspection method of the present invention performs a step of giving the electric motor an instructing for rotating a foot shaft in a reverse direction and checking whether the foot shaft is rotating in the reverse direction, and a step of checking whether hydraulic pressure acting on the hydraulic pump has reached a predetermined pressure level. By checking a rotating direction of the electric motor, it is possible to check electrical connections. By checking the hydraulic pressure, it is possible to check whether there is any trouble in a hydraulic system. Namely, the present invention can perform an electrical connection check and a hydraulic pressure check in a collective fashion.

Inspection method for inspecting electric drive apparatus

A first exemplary aspect of an embodiment of the present invention is a phase-locked loop circuit including: a voltage-current converter that converts a control voltage into a control current, the control voltage generated according to a phase difference between an input pulse signal and a feedback pulse signal fed back from an output side of a current controlled oscillator; the current controlled oscillator that generates an output pulse signal having a frequency according to the control current; a current detection unit that detects the control current; and a frequency range switch that switches a frequency range of the output pulse signal according to the detected control current.

Phase-locked loop circuit

A PLL circuit includes first and second charge pump circuits controlling an output voltage according to an output signal of a phase comparator, a first filter filtering out predetermined frequency component included in a signal generated according to current output from the first charge pump circuit, and outputting the signal as a first voltage signal, a second filter inputting a current output from the second charge pump circuit and outputting a predetermined constant voltage as a second voltage signal, a voltage control unit outputting a third voltage signal according to a comparison result between the first voltage signal output from the first filter and a reference voltage signal, and a voltage controlled oscillator that has a first low gain property, a second low gain property, and a high gain property, and is controlled by the first to third voltage signals to generate an oscillating frequency.

PLL circuit with VCO gain control

An ECU of a night vision system stores small obtained images of provisional targets as six templates depending on the distance from infrared cameras, and selects one of the templates depending on the distance up to an actual object. Using the selected template, the ECU performs template matching on images obtained by the infrared cameras, and calculates coordinates of the inspection target. The ECU compares the calculated coordinates of the inspection target and stored reference coordinates with each other, and determines mounted angles of the infrared cameras.

Vehicle vicinity monitoring apparatus

A pulse width modulation circuit comprises a multiphase clock generation section which generates multiphase clock signals based on a reference clock, and a pulse width modulation signal generation section which generates pulse width modulation signals based on input data and on multiphase clock signals generated by the multiphase clock generation section. The multiphase clock generation section has a phase-locked loop circuit and a clock selection circuit which selects an arbitrary clock signal from among the multiphase clock signals and outputs the selected clock signal to the phase-locked loop circuit as a feedback clock.

Pulse width modulation circuit and multiphase clock generation circuit

There is provided a lock detection circuit for optimizing a lock detection time and an unlock detection time of a PLL circuit. The present invention has counters and for inputting and counting feedback signals and reference signals inputted to a phase comparator of a PLL circuit ; a comparison circuit for inputting and comparing count values of the counters and and outputting a control signal in an active state when the count value of the counter is a first value and the count value of the counter is the first value; a counter for counting the feedback signals when the control signal outputted from the comparison circuit is active; and a decision circuit for outputting an output signal of a value showing a lock state when a count value of the counter reaches a second value. The comparison circuit resets the counter when the count value of the counter is the first value and the count value of the counter is not the first value.

Growing community of inventors

Tokyo, Japan

Yoshitaka Hirai