Fujitsu Corporation

Fujitsu Semiconductor Limited

Socionext Inc.

Fujitsu Microelectronics Limited

Yoshitaka Aiba

Mitsutaka Sato

Tetsuya Fujisawa

Hirohisa Matsuki

Ryuji Nomoto

Toshio Hamano

Masamitsu Ikumo

Yoshiyuki Yoneda

Yutaka Makino

Masaaki Seki

Noriaki Shiba

Tadahiro Okamato

Hiroshi Inoue

Junichi Kasai

Yasunori Fujimoto

Yoshihiro Kubota

Akira Okada

Seiichi Orimo

Kazuyuki Imamura

Yoshitsugu Katoh

Kaname Ozawa

Mitsuo Abe

Osamu Igawa

Jun Tsukakoshi

Keiji Nosaka

Yoshiyuki Yonoda

A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.

Semiconductor device having a high frequency external connection electrode positioned within a via hole

Semiconductor device having a high frequency electrode positioned with a via hole

A semiconductor device includes a semiconductor substrate having a main surface in which a semiconductor element region where a plurality of functional elements are formed is formed; a multilevel wiring layer disposed on the main surface of the semiconductor substrate; a first organic insulating material layer disposed on the multilevel wiring layer; a groove that penetrates the multilevel wiring layer on a scribe region that surrounds the semiconductor element region; and an organic insulating material that is spaced from the first organic insulating material layer and disposed in the groove.

Semiconductor device and method for making the same

A semiconductor device includes a first semiconductor chip () having a first terminal () on one surface, a second semiconductor chip () which is larger than the first semiconductor chip () and on which the first semiconductor chip () is stacked and which has a second terminal () on one surface, an insulating layer () formed on a second semiconductor chip () to cover the first semiconductor chip (), a plurality of holes () formed in the insulating layer () on at least a peripheral area of the first semiconductor chip (), a via () formed like a film on inner peripheral surfaces and bottom surfaces of the holes () and connected electrically to the second terminal () of the second semiconductor chip (), a wiring pattern () formed on an upper surface of the insulating layer (), and an external terminal () formed on the wiring pattern ().

Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same

A semiconductor device with a WLP structure that enables the improvement of heat resistance. A dam layer which spreads over a PI film and an Si substrate for a chip is formed between the Si substrate and a sealing resin so as to surround the chip on all sides. A material for the dam layer is selected so that good adhesion will be obtained between the dam layer and the Si substrate, between the dam layer and the PI film, and between the dam layer and the sealing resin. As a result, even if a crack appears at a portion on a side of the semiconductor device where the Si substrate and the sealed resin are joined in a heating environment, the crack does not run inside the dam layer. This prevents the peeling of the sealing resin or peeling inside the chip and the performance of the semiconductor device is maintained.

Semiconductor device and method for fabricating the same

A semiconductor device comprises a semiconductor chip, a wiring layer formed on the semiconductor chip, a column electrode connected at a first end to the wiring layer, and an encapsulation resin formed on the semiconductor chip. In the semiconductor device, the column electrode is provided with a second end, opposite to the first end, projecting from the encapsulation resin, and an external connection member is connected to the column electrode at the second end so that the external connection member is separate from a surface of the encapsulation resin.

Semiconductor device and method of manufacturing the semiconductor device

To provide a semiconductor device with high performance and reliability, in which peeling off an interconnection layer caused due to peeling off of a resin film at a land part is suppressed and thus electrical break down is prevented, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate (e.g., a silicon wafer); an insulating filmformed on the semiconductor substratea conductive layerformed on the insulating filmthe conductive layerformed of an interconnection partand a land partwhich connects the interconnection partto an external terminaland a resin filmcovering the conductive layerwherein the resin filmis in contact with the insulating filmat least at a part of the land partby passing through the conductive layer

Semiconductor device and manufacturing method for the same

A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.

Method of designing circuit board

A semiconductor device including a semiconductor element having an electrode pad, a mounting terminal for mounting a substrate, an adhesive layer provided on the semiconductor element, and a wiring electrically connecting the electrode pad to the mounting terminal. The wiring includes a metal foil and a metal film layer. The entire metal foil is in contact with the adhesive layer, and the metal film layer is in contact with the electrode pad.

Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal

There are provided a sealing insulating film that is formed on a substrate and melted at a first heating temperature to have a flowability, and external terminals that are formed on the substrate, and connected to other electronic device at a second heating temperature higher than the first heating temperature, and surrounded by the sealing insulating film.

Light signal processing system

In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.

Semiconductor device configured to be surface mountable

A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

External connection terminal and semiconductor device

A plurality of semiconductor chips are incorporated in a one-piece package so as to substantially increase a mounting area of a semiconductor device so that the semiconductor device can be provided with the projection electrodes having a structure which enable the semiconductor device to be mounted by a conventional surface mounting technique. A redistribution layer interconnects and integrally holds the plurality of semiconductor elements. A plurality of projection electrodes are provided on the redistribution layer for surface mounting. The plurality of semiconductor chips are rendered to be different kinds so that the plurality of different kinds of semiconductor chips together provide a complete function. The plurality of semiconductor chips may be rendered to be the same kind so as to reduce a mounting area of the semiconductor chips as a whole.

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Kawasaki, Japan

Yoshitaka Aiba