Lattice Semiconductor Corporation

Yoshita Yerramilli

Wei Han

David Lee Rutledge

Loren McLaury

Warren Juenemann

Mose Wahlstrom

In one embodiment of the invention, an integrated circuit such as a programmable logic device includes volatile memory, nonvolatile memory, and a data shift register for reading data from the nonvolatile memory and for reading data from and writing data to the volatile memory. A built in self test (BIST) circuit is operable to test the nonvolatile memory without the data shift register reading data from the nonvolatile memory. The BIST circuit may include a finite state machine for performing at least one of the following tests on the nonvolatile memory: bulk erase, bulk program; margin bulk program; and/or margin bulk erase. A memory controller responsive to the finite state machine is operable to write data to and read data from the nonvolatile memory during testing of the nonvolatile memory.

Programmable logic device with built in self test

An apparatus for generating round-key words in accordance with a Rijndael algorithm. In one embodiment of the invention, the apparatus includes (a) a key expansion register block, having a key expansion register adapted to receive a final cipher key of a key expansion schedule in accordance with the Rijndael algorithm; (b) a round constant generator; (c) a first XOR adder adapted to add a first word of the key expansion register to a second word to generate and provide a first sum to the key expansion register block; (d) a transformation block adapted to generate a transformed word based on the first sum and the current round constant over four counts of a first cyclical counter; and (e) a second XOR adder adapted to add the transformed word to the first word of the key expansion register to generate and provide a second sum to the key expansion register block.

Key generation for advanced encryption standard (AES) Decryption and the like

Various techniques are described to test memory arrays of a programmable logic device (PLD). In one example, a PLD includes a first memory array. The PLD also includes a plurality of sense amplifiers adapted to read a plurality of data values stored by the first memory array and provide a plurality of data signals corresponding to the data values. The PLD further includes a test circuit adapted to test the first memory array. The test circuit is coupled with the sense amplifiers and adapted to compare the data signals with a test signal to provide a pass/fail signal. In addition, the PLD includes a second memory array. The PLD also includes a data shift register adapted to test the second memory array.

Methods and devices are disclosed herein to provide improved techniques for securing configuration data stored in non-volatile memories of programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a plurality of configuration data. A plurality of security fuses are adapted to store a plurality of logic states. Control logic is adapted to selectively secure the configuration data within the non-volatile memory based on the logic states stored in the plurality of security fuses.

Selective programming of non-volatile memory facilitated by security fuses

In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data. A plurality of configuration memory cells within the PLD is adapted to receive configuration data transferred from the non-volatile memory. The PLD further includes control logic adapted to determine based on the logic states of the first and second bits stored in the non-volatile memory and prior to any transfer of the configuration data whether to transfer the configuration data from the non-volatile memory to the configuration memory cells.

Selective loading of configuration data into configuration memory cells

Systems and methods are disclosed herein to provide improved techniques for loading of configuration memory cells in integrated circuits, such as programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data; a plurality of configuration memory cells; and control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells.

Growing community of inventors

Hillsboro, OR, United States of America

Yoshita Yerramilli