Hitachi, Ltd.

Hitachi Computer Engineering Co., Ltd.

Microcomputer Engineering Ltd.

Yoshiro Shiroyanagi

Akira Kurano

Katsunori Nakamura

Hisaharu Takeuchi

Akira Yamamoto

Hisashi Takamatsu

Shigeru Kishiro

Toshio Nakano

Kenji Yamagami

Masafumi Nozawa

Hiroyuki Kitajima

Shizuo Yokohata

Haruaki Watanabe

Shigeo Honma

Kosaku Kambayashi

Toshiaki Tsuboi

Kiyoshi Hisano

Shuji Sugimoto

Toru Nishigaki

Masahiro Nakayama

Yoshiaki Muto

Tomohito Ogino

Norio Hamada

In a magnetic disk controller equipped with a cache memory for disks, the controller in accordance with the present invention includes high order paths for data transfer between a high order channel apparatus and the cache memory through a certain one of a plurality of channel adaptors, low order paths for data transfer between a low order device, e.g. a magnetic disk device, and the cache memory through a certain one of a plurality of device adaptors and a path for data transfer betweeen the low order device and the channel cevice without passing through the cache memory by selecting empty device adaptor and channel adaptor by the switching operation of a switch. When an interrupt is generated from the device, data transfer can be made easily even when the high order path and the low order path are busy, and path utilization efficiency can be improved.

Controller of paths for data transfer in system having external memory

A storage system connected to host processors through data transfer paths includes at least one storage unit for moving a head for reading/writing the data relatively to a storage medium to read/write the data from/to the storage medium, and a controller for controlling the data transfer between the host processors and the storage units. The controller obtains and stores, every data transfer path, the information relating to the delay time which occurs when transferring the data through the data transfer path of interest. When an I/O request is issued from the host processor, in accordance with the measured information of the delay time in the data transfer paths, a request for positioning the head near the position on the storage medium in which the data is stored which is to be read/written is issued. In addition, when posting the release of the wait state to the host processors which had issued the I/O requests and are made wait the completion of the processings for other I/O requests, the order of issuing the notification is determined in accordance with the delay time in the data transfer paths which are permitted to be used in order to process the I/O requests.

Storage system and method of remotely controlling the same

In a control unit having a external storage device, a method for selecting a loading method of data stored in the cache memory into the cache memory in accordance with an access pattern to the data, and an apparatus therefor are disclosed. The selection of the loading method is selection of control mode or procedure in accordance with the loading method, and it is attained by a learn function.

Memory controller with a cache memory and control method of cache memory

When recording records into the IC memory group of a magnetic disk subsystem the records being composed of a count area of a fixed length, key area of a variable length and a data area of a variable length, data of a special format which is judged by ECC check to be an abnormal data is written at the top of the count area in each record. When reading an object record from the IC memory group, it is judged by ECC check whether or not the read data is an abnormal one. When the read data is judged to be an abnormal one, the read data is compared with the data of special format, and when there is found a coincidence between them, it is recognized that the read data are at the top of the count area. When writing data, data which are judged by ECC check to be a normal are suffixed to data which are judged by ECC check to be abnormal. When the read data are judged by the ECC check to be abnormal and judged by a next ECC check to be normal, it is recognized that the read data are at the top of the count area.

Method for writing/reading of data in magnetic disk subsystem

A control system for a disk cache memory is disposed between a main memory unit and a disk unit for storing a record of data from the disk unit. The control system is designed such that when an input/output instruction is issued from a CPU while data loading is being performed from the disk unit to the cache memory, it interrupts the data loading once so that an input/output instruction from the CPU can be executed, thereby considerably reducing the time of wait for execution of the input/output instruction.

Control system for interruption long data transfers between a disk unit

When a disk controller receiving an access from a host computer to a disk device is connected with a disk connection device, if a relevant disk is used by another disk controller, positioning data for seek, set file mask and set sector are queued in a common memory. When the relevant disk becomes free, the disk controller reads the queued information and requires the disk device for positioning. A request of a reconnection with the host computer is issued from the disk controller informed by the disk unit, which has finished positioning at the position specified by the positioning data, search of an aimed record and a read/write operation of transmitted data are effected without any new intervening of an access program of the host computer.

Multiple control system for disk storage and method for realizing same

A method for controlling to keep off defects in a magnetic disk apparatus while has a plurality of magnetic disks and defect position information is recorded in each of tracks on each magnetic disk to keep off a defect in writing records in each track. Positional information about defects on all the tracks belonging to a cylinder of the magnetic disk apparatus is recorded in each of the tracks, and records are written in each of the tracks while keeping off the defects on the basis of the recorded positional information about the defects.

Method for controlling to keep off defects on magnetic disks

The present invention relates to a computer system having a disk cache unit between a disk unit and the main storage unit. Ordinarily, the data transfer processing is carried out between the disk unit and the disk cache unit and between the disk cache unit and the main storage unit in this case under control of a director. The present invention is characterized by enabling these two data transfer operations to be executed in parallel and to prevent the director from becoming the bottleneck of the processing due to the concentrated processing requests. For this purpose, the present invention provides for a data transfer between the disk cache unit and a disk unit while a data transfer is taking place between the main storage unit and the disk cache unit.

Method and system for concurrent data transfer disk cache system

An apparatus for controlling data transfer between a rotary storage device such as a magnetic disk having a plurality of heads for different tracks and another storage device such as a disk cache includes a plurality of transfer circuits for the purpose of simultaneous data transfer to and from a plurality of tracks. The transfer circuits operate concurrently with and independently of each other to transfer data therethrough and other than noting the regions to be skipped over, ignoring data format on the track. The apparatus is suitable for preloading a disk cache from a disk.

Control apparatus for simultaneous data transfer

There is disclosed an error recovery apparatus and method for a data processing system having (1) a peripheral unit, for instance, a magnetic disc unit, for storing data in a plurality of blocks each having a unique address, (2) a main memory for storing data read from the peripheral units, and (3) a controller for controlling the transfer of the data blocks from the peripheral unit to the main memory by execution of a single channel command word (CCW) chain. When an uncorrectable error occurs in the transfer of a second or subsequent data block of the plurality of data blocks (not the first data block), the processor produces a new CCW chain to re-read the data block in error in addition to all the data blocks subsequent to the data blocking error and store these data blocks in the memory under the control of the new CCW chain.

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Odawara, Japan

Yoshiro Shiroyanagi