Nec Corporation

Yoshiro Goto

Kiyotaka Imai

Naohiko Kimizuka

Takeshi Toda

In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

Integrated circuit device with switching between active mode and standby mode controlled by digital circuit

A thermal oxide film is formed on a silicon substrate, a polysilicon film is formed on the thermal oxide film, and further a patterned photoresist film is formed on the polysilicon. The polysilicon film and the thermal oxide film are etched using the photoresist film as a mask so as to form a gate electrode and a gate oxide film. The photoresist film is removed therefrom, and a thermal oxide film is formed in the circumference of the gate electrode, thereby to restore a constriction formed in the gate oxide film. A part of the thermal oxide film which corresponds to the gate electrode and another part thereof which corresponds to the semiconductor substrate are removed therefrom, and a side wall nitride film which adhere to the silicon substrate is formed on a side wall of the gate electrode. Thereafter, a source and drain diffusion layers corresponding to the gate electrode are formed on the silicon substrate, thereby to form metal wiring.

Semiconductor device and method of manufacturing the same

The present invention provides a manufacturing method of a semiconductor device having a single semiconductor substrate, for forming a first processing circuit portion and a second processing circuit portion having mutually different thicknesses of gate oxide films on the single semiconductor substrate including the steps of: forming a first gate oxide film over the semiconductor substrate; sequentially forming an insulating film and a first conducting layer over the entire surface of the first gate oxide film; eliminating those portions ranging from the first gate oxide film to the first conducting layer, which portions are included within an element forming region of the first processing circuit portion; and forming, only in the element forming region of the first processing circuit portion, a second gate oxide film having a thickness different from that of the first gate oxide film.

Manufacturing method of semiconductor device having different gate oxide thickness

Producing method for a semiconductor device in which, for producing CMOS transistors of plural sorts, for example, dual power source transistors, having an added ROM unction, the number of times of ion implantation and resist pattern formation can be reduced to reduce the number of producing process steps. In producing a semiconductor device comprised of five sorts of MOS transistors, namely thin-film CMOS transistors (area A of FIG.,), thick-film CMOS transistors (area B of FIG.,) and an ROM code transistor (area C of FIG.,), ion implantation for forming an inversion layer (,of FIG.,) on a channel surface of the ROM code transistor and the ion implantation for adjusting threshold value voltage of P channel of the CMOS transistor are carried out in the same process step (process (d) of FIG.,). Also, the ion implantation for adjusting threshold value voltage of N channel of the thin-film CMOS transistor is effected using a resist pattern (,of FIG.,(,)) for the formation of a gate oxide film of the thin-film C MOS transistor (step (g) of FIG.,).

Method for producing semiconductor device

In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer under the gate electrode. After that p-type diffused layers to serve as source and drain are formed by ion implantation through the n-type diffused layers, and the implanted impurities are activated. In consequence, impurity concentration at the substrate surface becomes lower in the section right under each end of the gate electrode than in the gate middle sections. This measure brings about suppression of the short channel effect inherent to conventional buried-channel MOS transistors and makes it possible to shorten the physical gate length.

Buried-channel MOS transistor and process of producing same

A semiconductor device is fabricated by steps of forming, by atmospheric pressure CVD or low pressure CVD without using plasma, a first insulating layer that covers a semiconductor substrate having a protruded and recessed surface; forming, by bias plasma CVD using an electron cyclotron resonance process, a second insulating film that covers the first insulating layer; and planarizing the second insulating film by a CMP process. In this way, the time required for planarizing a surface of the semiconductor substrate by the CMP can be reduced.

Method for fabricating semiconductor device with planarization step

In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer under the gate electrode. Then p-type diffused layers to serve as source and drain are formed by ion implantation through the n-type diffused layers, and the implanted impurities are activated. In consequence, impurity concentration at the substrate surface becomes lower in the section right under each end of the gate electrode than in the gate middle section. This measure brings about suppression of the short channel effect inherent to conventional buried-channel MOS transistors and makes it possible to shorten the physical gate length.

In a method for manufacturing a CMIS transistor, after gate electrodes are formed, deep P type impurity regions and shallow N type impurity regions are formed within both of a PMOS area and an NMOS area. Then, after sidewall insulating layers are formed on sidewalls of the gate electrodes, P type impurity ions are introduced into the PMOS area and N type impurity ions are introduced into the NMOS area.

Method for manufacturing LDD type MIS device

An electrically programmable read only memory device store data bits in the form of electric charges accumulated in floating gate electrodes of the memory cells, and a spin-on glass film is incorporated in an inter-level insulating film structure over the memory cells so as to create a smooth surface for wirings, wherein a silicon oxynitride film is inserted between the floating gate electrodes and the spin-on-glass film for preventing the accumulated electric charges from undesirable ion-containing water diffused from the spin-on-glass film.

Growing community of inventors

Tokyo, Japan

Yoshiro Goto