Kabushiki Kaisha Toshiba

Samsung Electronics Co., Ltd.

Tokyo Shibaura Denki Kabushiki Kaisha

Yoshio Wada

Kenji Hara

Katsuji Fujita

Hideaki Ito

Hiroshi Sadamatsu

Kazuki Takaki

A circuit for a fast Fourier transform (FFT) operation is provided. The FFT operation circuit includes a plurality of butterfly operation units connected in series. Each of the plurality of butterfly operation units reads a signal in the order in which the plurality of butterfly operation units perform complex multiplication, addition, and subtraction, performs complex multiplication of each sequentially read signal by a complex coefficient corresponding to an FFT length and the stage number of the butterfly operation unit, and performs complex addition and subtraction with the complex multiplied signal. In this way, without disposing a plurality of operation circuits corresponding to a radix, FFT operations corresponding to a plurality of FFT lengths can be performed.

Circuit for fast fourier transform operation

A method and apparatus for compensating for a delay in the propagation of a plurality of signals via different signal paths, i.e., a skew compensation method, are provided. The apparatus includes a processing circuit which performs a data processing operation on input data, and a reset adjustment circuit which maintains a reset state of the processing circuit for a time period when a reset signal that initializes the processing circuit is received.

Circuit block and circuit system having skew compensation, and skew compensation method

An ultra-wideband transmitter and receiver, and a ultra-wideband wireless communication method, which perform ultra-wideband wireless communication by a low-speed digital circuit having a low power consumption and controlling the effect of a multi-pass. In ultra-wideband transmitter, delay time controller generates and inputs a periodic pulse to a first matched filter, outputs the periodic pulse to a second matched filter when data to be transmitted are at a first level of a binary logic level, and outputs the periodic pulse to a third matched filter when the data to be transmitted are at a second level of the binary logic level. The first matched filter receives the periodic pulse from the delay time controller and outputs a reference signal for data determination the second matched filter receives the periodic pulse from the delay time controller and outputs a first data signal earlier than the reference signal by a predetermined time. The third matched filter receives the periodic pulse from the delay time controller and for outputs a second data signal later than the reference signal by a predetermined time. An adder adds outputs of the first, second, and third matched filters to each other and outputs an added signal, and an antenna section receives the added signal from the adder and radiates the received added signal into the air.

Ultra-wideband transmitter and receiver, and ultra-wideband wireless communication method

A signal demodulator apparatus comprises: an input terminal (11) for inputting an external signal; a delay line (12) connected to the input terminal, for outputting a first delay signal obtained by delaying the external signal by a predetermined time; a phase corrector (13) responsive to the first delay signal outputted by the delay line, for correcting phase of the first delay signal on the basis of a phase difference detection signal and outputting the first phase-corrected delay signal as a second delay signal; and a phase difference detector (16, 15, 19, 20) for detecting a phase difference between the second delay signal outputted by said phase corrector and the external signal inputted through the input terminal and for outputting the phase difference detection signal to the phase corrector to correct the phase difference to a predetermined value. Whenever the delay time of the delay signal disperses due to a manufacturing error or a change with the lapse of time of the delay line (12), it is possible to automatically correct an offset of the phase difference from a normal value.

PAL chroma signal demodulating apparatus

Video signal delay circuit having self adjusting gain

Since the resistor is inserted between each of the emitters of the transistors to which the comparison voltage is applied and each of the collectors of the differential pair of transistors, a positive feedback is applied at different points where a differential input voltage is increased from the negative and it is decreased from the positive, and thus the voltage comparator circuit has the hysteresis characteristics. It is therefore possible to reliably have the hysteresis characteristics of a narrow range of voltage of 100 mV or less (for example, several tens of millivolts) without increasing the number of elements in use or depending upon the value of k.multidot.T/q (k is the Boltzmann's constant, T is an absolute temperature, and q is an amount of charge of electrons).

Voltage comparator circuit having hysteresis characteristics of narrow

A detector circuit comprises demodulating means for demodulating an input signal in accordance with a carrier wave applied to the demodulating means, current attenuating means coupled with the demodulating means and for attenuating a signal from the demodulating means while keeping the information contained in the signal intact, and capacitor means, coupled with the output of the current attenuating means, for smoothing a waveform of an output signal of the current attenuating means.

Detector circuit including current attenuating circuit and capacitor

A switch circuit is comprised of first and second NPN transistors, the collectors of which are interconnected and the emitters of which are respectively connected to an input terminal and a reference voltage, third and fourth PNP transistors connected between the bases of said first and second transistors and a power source voltage, and fifth and sixth NPN transistors connected between the bases of the third and fourth transistors and ground. Seventh and eighth PNP transistors, connected between the power source and ground, are further provided, with their ON and OFF states being controlled by a control signal applied to the bases thereof. The bases of the fifth and sixth transistors are respectively connected to the collectors of the seventh and eighth transistors. The fifth and sixth transistors are ON/OFF controlled by the collector currents of the seventh and eighth transistors, respectively.

Growing community of inventors

Yokohama, Japan

Yoshio Wada