Kabushiki Kaisha Toshiba

Yoshio Sakata

Masami Taoda

32-bit image data transferred through an image data bus is input to a thinning out circuit through a bus I/F, and is thinned out by the thinning out circuit to have an active data width of 24 bits. The 32-bit data including the active data width of 24 bits obtained by the thinning out operation is supplied to a line buffer block. The line buffer block has a data width equal to or larger than the maximum bit width of the image data bus. The 32-bit data supplied to the line buffer block is directly written in the line buffer block. The data written in the line buffer block is repetitively shifted by a shift register block according to the active data width of 24 bits.

Parallel/serial data conversion system

An image information processing apparatus includes an image memory having a page memory area for storing image information and a FIFO memory area which is provided integrally with the page memory and a read/write operation of which is controlled independently of the page memory area. Coded image information supplied from a recording unit is transferred to a codec circuit through the FIFO memory area and decoded by the codec circuit. The decoded information is stored in the page memory area.

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Yokohama, Japan

Yoshio Sakata