Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Vlsi Engineering Corp.

Hitachi Engineering Co., Ltd.

Hitachi Elevator Engineering & Service Co., Ltd.

Hitachi Building Systems Engineering and Service Co., Ltd.

Yoshio Sakai

Osamu Minato

Toshiaki Masuhara

Naotaka Hashimoto

Toshiaki Yamanaka

Hiromi Inaba

Satoshi Meguro

Yoshifumi Kawamoto

Toru Kaga

Tokuo Kure

Toshiaki Kurosawa

Kiyoshi Nakamura

Eiji Takeda

Norio Suzuki

Takashi Hashimoto

Katsuhiro Shimohigashi

Takeki Ando

Hideaki Takahashi

Hideo Sunami

Atsuyoshi Koike

Kenji Yoneda

Makoto Motoyoshi

Kiyofumi Uchibori

Seiya Shima

Atsuya Fujino

ShinIchiro Kimura

Masao Nakazato

Toshimitsu Tobita

Yuji Toda

Hiroaki Kuroha

Mitsumasa Koyanagi

Koichiro Ishibashi

Shuji Ikeda

Toshio Sasaki

Shinji Shimizu

Masanobu Miyao

Nobuyuki Moriwaki

Shoji Hanamura

Kouichi Nagasawa

Noboru Arabori

Shigeru Honjyo

Masato Suzuki

Shinichiro Kimura

Masaharu Kubo

Hideo Nakamura

Soshiro Kuzunuki

Kotaro Hirasawa

Takashi Nishida

Sadao Hokari

Norikazu Hashimoto

Tokumasa Yasui

Akiteru Ueda

Masakatsu Tanaka

Kenzi Yoneda

Yuzo Morita

Takaaki Ueshima

Tsutomu Sano

Keizo Suzuki

Akihiro Shimizu

Isao Yoshida

Kouki Noguchi

Yoshiaki Kamigaki

Hiroshi Takenaga

Ryo Nagai

Sadayuki Okudaira

Shinpei Iijima

Yoshimune Hagiwara

Minoru Nagata

Hiroo Masuda

Tetsuya Hayashida

Shigeru Nishimatsu

Katsuro Sasaki

Shigeta Ueda

Hisao Katto

Chuichi Saito

Hideaki Kato

Terunori Warabisako

Masaaki Aoki

Satoshi Fukuda

Yasunobu Kosa

Hisakatsu Kiwaki

Mutsuhiro Terunuma

Kotaro Nishimura

Takeaki Okabe

Michio Fujiwara

Katsu Komuro

Kazuhiro Sakata

Seiji Yasunobu

Mineo Katsueda

Kazuhira Ojima

Mitsuyuki Honbu

Kazutoshi Ashikawa

Shigeru Honjo

Nobuo Mitsui

Seiichi Isomae

Kiyotsugu Ueda

Seikichi Masuda

Shin-ichi Muramatsu

Mitsuo Ito

Masanobu Itoh

A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

Semiconductor memory device

Elevator group supervisory control method and system for group supervisory control of a plurality of elevators serving a plurality of floors. The method and apparatus of the invention permits the inputting of qualitative requests (guidance), from the user, concerning elevator operation into the group supervisory control system. Qualitative requests concerning elevator operation are set in the form of guidance (or request) targets. The thus set request targets are converted into control targets for the elevators. Actual group supervisory control is executed using the control targets.

Method and system of controlling elevators and method and apparatus of

The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type or of n-type and p-type polycrystalline silicon films, respectively, and electrical connections are formed between the drain regions of the first and second p-channel load MISFETs with that of the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. Also, there are formed electrical connections between the polycrystalline silicon gate electrodes of the first and second load MISFETs with that of drain regions of the second and first drive MISFETs, through the poly-Si gate electrodes of the first and second drive MISFETs, in each memory cell of the SRAM, respectively, furthermore.

Semiconductor integrated circuit device

A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type and p-type polycrystalline silicon films, respectively, and the drain regions of the first and second p-channel load MISFETs are electrically connected to the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. The polycrystalline silicon gate electrodes of the first and second load MISFETs are respectively electrically connected to the drain regions of the second and first drive MISFETs in each memory cell of the SRAM, furthermore.

A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.

Semiconductor memory device having stacked capacitors

A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.

The present invention relates to a group control elevator system which has been adjusted to operate in response to a state of utilizing elevator cars. In a group control elevator system which carries out a control of allocating elevator cars to elevator car calls for serving many floors by using an evaluation function having a plurality of variable parameters, targets for elevator control performance are inputted, a traffic flow to which elevator car demand belongs is judged, variable parameters to be adjusted which have been set in advance for each combination of said targets and traffic flows are stored, stored variable parameters are adjusted, adjustment sequence of variable parameters to be adjusted is stored, and a plurality of variable parameters are sequentially adjusted according to the stored sequence. By the above arrangement, only desired parameters to be adjusted are selected and adjusted out of a plurality of variable parameters for desired targets and traffic flows. Accordingly, an increase in time required for adjustment can be restricted even if there has been an increase in the number of variable parameters to be adjusted.

Group control elevator system for automatically adjusting elevator

An elevator system which is provided with power converters, electric motors supplied with power from the power converters, and a torque distributing section having functions for determining allocation of output power from the power converters on the basis of a required torque, by which an elevator is operated on the basis of functions selected in accordance with the operation mode. The system is able to save power in the elevator operation and also improve control functions and increase system capacity.

Elevator system

Method of fabricating stacked capacitor cell memory devices

Elevator group supervisory control method and system for group supervisory control of a plurality of elevators serving a plurality of floors. The method and apparatus of the invention permits the inputting of qualitative requests (guidance), from the user, concerning elevator operation into the group supervisory control system. Qualitative requests concerning elevator operation are set in the form of guidance (or request) targets. The thus set request, targets are converted into control targets for the elevators. Actual group supervisory control is executed using the control targets.

An elevator control system for controlling movement of cages up and down in accordance with the situation of waiting persons in landing places or passengers in the cages detected by image pickup devices and other detecting devices includes first and second image processors, the image processing level of the second image processor being not lower than that of the first image processor. The system further includes an elevator controller for controlling movement of the cages up and down, the elevator controller including a device for applying the result of image processing performed by the first image processor to the control of the cages, and a device for applying the result of image processing performed by the second image processor to the control of the cages when the image processing is carried out based on the result of image processing performed by the first image processor and other information pertaining to passengers and waiting persons detected by the other detecting devices.

Elevator control system with image pickups in hall waiting areas and

A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Semiconductor memory

Growing community of inventors

Tsukui, Japan

Yoshio Sakai