Hitachi, Ltd.

Hitachi Computer Engineering Co., Ltd.

Hitachi Tokyo Electronics Co., Ltd.

Yoshio Oshima

Toru Ohtsuki

Sako Ishikawa

Masaharu Fukuta

Yukiharu Akiyama

Hideaki Yabe

Michitaka Yamamoto

Yasutaka Yamada

Kazuo Hibi

Hideki Hidaka

Toshinori Kuwabara

Nobuyuki Shimura

Yasushi Ishii

Kunihiro Tsuchiya

Instead of translation from a space address to a segment table origin address (STO) by an ordinary instruction, translation to the STO is done by a space base register modify instruction which uses an instruction to modify the content of the space register, and the result thereof is used for the operand address calculation of the instruction to the operand data fetching. The present system eliminates the need for additionally providing for hardware of an operand fetch unit hardware for the translation from the space address to the STO, memory for storing translation pairs of the space addresses and the STO's and the table look-up of the translation pairs. Thus, degradation of performance is minimized with less hardware.

Multiple virtual addressing using/comparing translation pairs of

An information processing apparatus having at least one processor and a main storage, accessed by the processor, and capable of providing a plurality of logical information processing apparatus by logically partitioning the information processing apparatus. The information processing apparatus includes a main storage partitioned into a plurality of memory areas, each of the memory areas corresponding to one of the plurality of logical information processing apparatus. The information processing apparatus further includes a first storage unit for storing identification information for each of the memory areas identifying the logical information processing apparatus allocated to each memory and a read unit for reading the identification information from the first storage unit when the main storage is to be accessed by one of the plurality of logical information processing apparatus. Each of the plurality of logical information processing apparatus possesses a unique identification information. The information processing apparatus further includes a comparison unit for comparing the identification information read by the read unit with the identification information of the one logical information processing apparatus which accesses the main storage and a unit for determining if the access to the main storage is allowed, in accordance with the comparison result of the comparison unit. Access by the one logical information processing apparatus is canceled if the determining unit determines the access is not allowable.

System using selected logical processor identification based upon a

The present invention relates to a ball bonding technique using an insulated wire in assembling a semiconductor chip in which the ball is formed at the end of an insulated wire by an electrical discharge and the insulation at a portion of the wire to be bonded a predetermined distance from one end of the wire is removed by an electrical discharge.

Method and apparatus for wire bond

Method and apparatus for wire bonding

A wire bonding method and apparatus comprising a comparator wherein a difference between a position command signal for displacing a moving member such as, for example, a wire bonding tool, and a position signal obtained from a sensor for detecting the position of the moving member is compared with a predetermined threshold or reference value so that a stopping of the moving member, caused by an external force such as a contact therewith with another member can be rapidly and accurately electrically detected. A wire bonding method and apparatus is useable for producing a semiconductor device.

wire bonding method and apparatus and method of producing semiconductor

An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.

Apparatus for decimal multiplication

A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted quotient read out from the quotient prediction table is used intact when the predicted quotient is correct while otherwise the predicted quotient is decremented by one, wherein the values stored in the quotient prediction table together with redundant bit are previously modified to (0110).sub.2 to (1111).sub.2 in the binary coded decimal representation. The multiple value register is selected by using three of the four bits of the modified predicted quotient, while upon determination of the quotient, the value used for modification is subtracted from the output value of the quotient prediction table to thereby derive the predicted quotient of one digit. With this arrangement, three of the four bits of the predicted quotient of one digit read out from the quotient prediction table can be used directly as the selection signal for selecting the relevant divisor multiple register.

Binary coded decimal number division apparatus

In preparation of addresses of a quotient prediction table used in a binary coded decimal number division scheme with predetermined bits of a dividend and a divisor in binary coded decimal representation, the addresses are modified with the redundant bits. The absolute bit number for the addresses is thus decreased, whereby data quantity and hence capacity of RAM required for implementing the quotient prediction table can be significantly reduced, while satisfactory function of the quotient prediction table being assured. The apparatus for the binary coded decimal number division is implemented inexpensively in a small size.

A multiplier device comprising hold means for holding the result of addition, block product means for producing k block products each having 2n bits, where n is an integer equal to or greater than 2, the k block products being formed by multiplying each block by n bits, k blocks being obtained by dividing a multiplicand at intervals of n bits from the least significant bit of the multiplicand, and adder means for adding two groups of block products to the output of the hold means, the two groups of block products consisting of alternate block products out of the k block products from the block product means.

Growing community of inventors

Tokorozawa, Japan

Yoshio Oshima