Kureha Kagaku Kogyo Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Oki Electric Industry Co., Ltd.

Toko International Patent Office

Yoshio Okada

Yuriko Igarashi

Tadashi Nakamura

Youichi Ohhira

Mitsuru Shimizu

Kazuhiro Watanabe

Syuso Fujii

Tomokazu Komazaki

Yasushi Nishimura

Yasuo Uehara

Masahiro Akatsu

Kuniaki Hino

Nobuo Ahiko

Yohichi Ohira

Kimio Okubo

Kenji Tsuchida

Toshimasa Namekawa

Hiroyuki Horii

Masaki Ogihara

Shozo Saito

Kiyofumi Sakurai

Katsuhiko Gunji

Hajime Shimamura

Kazushige Noguchi

Hisanori Ehara

Takashi Terauchi

Yutaka Igari

Toshikazu Yasuoka

Masao Iwata

Makoto Naoki

Kohichiro Shimizu

Masatoshi Hino

Shouichi Hoshi

Kazushige Nogichi

Kozyu Watanabe

Sadao Imada

A constant voltage generating device comprises a reference voltage generating circuit, a constant-current circuit unit and a current-to-voltage converting circuit unit. The reference voltage generating circuit generates a desired reference voltage. The constant-current circuit unit comprises a differential error amplifier to which the reference voltage generated by the reference voltage generating circuit is input as a reference potential, a first current controlling MOS transistor having a gate electrode to which an output of the differential amplifier is input, and a standard resistor serially connected to the first current controlling MOS transistor. The constant-current circuit unit generates a reference current to control a differential amplifier so that a constant current can be caused to flow therethrough. The current-to-voltage converting unit comprises a second current controlling MOS transistor constituting a current mirror together with the first current controlling MOS transistor of the constant-current circuit unit, and a current-to-voltage converting MOS transistor serially connected to the second current controlling MOS transistor and constituting a current mirror together with an active element unit current controlling MOS transistor of the differential amplifier.

Constant-voltage generating device

A surface-acoustic-wave filter couples a two-port surface-acoustic-wave resonator filter circuit coupled in parallel or in series with a two-port impedance circuit. The two-port impedance circuit has an impedance that creates a pole of attenuation, by making the open-circuit impedance of the surface-acoustic-wave filter equal to the short-circuit impedance. High attenuation over a wide range of stopband frequencies is obtained in this way, combined with steep roll-off between the passband and stopband.

Surface-acoustic-wave filters with poles of attenuation created by

A stripline resonator is constructed of a dielectric plate having a ground electrode formed on a side surface thereof, an open-ended .lambda./2 long stripline arranged on a top surface of the dielectric plate, an input terminal to which signals are inputted, said input terminal is connected to one end of the open-ended .lambda./2 long stripline, a first reactance element connected either in series or in parallel between the input terminal and the open-ended .lambda./2 long stripline, and a second reactance element connected at one end thereof to an opposite end of the open-ended .lambda./2 long stripline and at an opposite end to a ground electrode.

Stripline resonator

A semiconductor memory device includes a plurality of memory cell arrays, a plurality of decoders for decoding a first address of memory addresses, each of the decoders being connected to a corresponding memory cell array, and a plurality of sense amplifiers, each connected to a corresponding memory cell array. Also included are a decoder for decoding a second address of the memory addresses, the decoder being connected to every memory cell array, to be shared by every memory cell array, a plurality of redundancy memory cells, each of which is arranged for a corresponding memory cell array, and a plurality of programming circuits, each, arranged relative to a corresponding memory cell array to receive the first memory address and output a signal of a predetermined logic level corresponding to a defective memory cell in a memory cell array. Further, there is included a programmable decoder for receiving the second address and signal from the programming circuits, for changing a decoding state of the second address according to the logic level of the output signal from the programming circuits and for outputting a redundancy memory cell select signal which selects a redundancy memory cell in place of a specified defective memory cell.

Semiconductor memory device having redundancy memory cells

When data read out from a memory cell array is output to an external device through an output buffer, a first and a second address transition detector generate a first read control pulse signal and a second read control pulse signal in response to a change in an address signal. An operation for reading out data is controlled using the first and second read control pulse signals, such that when noise generated by a change in power source potential, due to a change in output, causes a possible detected change in the address signal, the first and second address transition detectors control the output buffer so erroneous operation is prevented.

Semiconductor memory device and method for controlling an output buffer

A protection circuit is inserted between a signal input pad and an internal circuit. The protection circuit includes a parasitic bipolar transistor which is obtained by forming high-impurity concentration semiconductor regions in the major-surface region of a substrate. In practice, it is hard to provide a parasitic bipolar transistor of a sufficiently large size, since the reduction of the size of a chip is a recent trend. With this in mind, a third semiconductor region serving as an electron-trapping region is formed in a region outside of the location where the parasitic bipolar transistor is formed. If an excessive voltage produced by ESD or the like is applied to the pad, and the excessive voltage uncontrollable by the parasitic bipolar transistor, the third semiconductor region absorbs the excessive voltage. In particular, where the current capacity of the parasitic bipolar transistor is small, the third semiconductor region reliably prevents electrostatic destruction of a circuit element. Accordingly, the protection circuit enables the parasitic bipolar transistor to be reduced in size, thus contributing to miniaturization of a chip. Moreover, the protection circuit is reliable in operation.

Protection circuit for use in semiconductor integrated circuit device

A semiconductor memory device comprises a sense amplifier, a reference potential terminal, a switching element, and control. The switching element is connected between sense amplifier and said reference potential terminal. The control generates and supplies a first column-selecting signal to the switching element to turn on and off switching element.

Semiconductor memory having improved sense amplifiers

First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad. The first impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the first and third impurity regions constitute a first bipolar transistor for input protection and the second impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the second and third impurity regions constitute a second bipolar transistor for input protection. The resistor and the first and second bipolar transistors constitute an input protection circuit.

Input protection circuit for semiconductor integrated circuit device

Disclosed herein is a process for selectively synthesizing the para-isomer of alkylbiphenyl in the alkylation of biphenyl with propylene or butene, employing zeolite having a molar ratio of SiO.sub.2 to Al.sub.2 O.sub.3 of not less than 10, as a catalyst.

Process for selectively alkylating biphenyl

An input protection circuit for MOS devices includes a first resistor and a first parasitic bipolar transistor connected between an input pad and an input buffer circuit of a MOS device. The input protection circuit for MOS devices further includes a second resistor and a second parasitic bipolar transistor connected at a preceding stage of the input buffer circuit so that the gate oxide film of the input buffer circuit can be protected from being damaged by static charges or a voltage which is accidentally generated, without increasing the pattern size of the first parasitic bipolar transistor.

Input protection circuit for MOS device

A semiconductor memory comprises a memory cell for storing data, a bit line pair for transfering the data, a sense amplifier for amplifying the data from the bit line pair, a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory, and a pair of constant voltage barrier transistors connected between the restore circuit and the sense amplifier for increasing the speed of sensing.

Semiconductor memory having barrier transistors connected between sense

A semiconductor device having an input protection circuit is disclosed. The semiconductor device includes a power-on reset circuit which generates a pulse having a pulse width determined according to an input surge, applied to an input terminal when an input voltage has risen to a preset level. In response to a pulse generated by the power-on reset circuit, a CMOS inverter supplies a predetermined voltage to the base of a bipolar transistor and controls the bipolar transistor so that it clamps an input voltage supplied thereto to a voltage level lower than the withstanding voltage of the internal circuit in a period corresponding to the pulse width. Thus, the input protection circuit constituted by the bipolar transistor clamps an input voltage, supplied by the input terminal to the internal circuit, to a predetermined level. In this invention, the control circuit activates the bipolar transistor at the time the input voltage rises and keeps it active while the power-on reset circuit is generating a pulse, causing an input surge to be bypassed through the bipolar transistor, during this period of time. Thus, the input voltage can be clamped to a level lower than the withstanding voltage of the internal circuit, protecting the internal circuit, even when a surge voltage higher than the withstanding voltage is generated.

Semiconductor integrated circuit with input protection circuit

A solvent for chromogenic dye-precursor material for pressure-sensitive recording paper sheet, comprising 50 to 80% by weight of p-monoisopropylbiphenyl and 50 to 20% by weight of hydrogenated terphenyl, and a pressure-sensitive recording paper sheet prepared by using the solvent.

Solvent for chromogenic dye-precursor material for pressure-sensitive

Disclosed herein are a substantially odorless solvent for a chromogenic dye-precursor material for a pressure-sensitive recording paper sheet, which comprises from 0 to 20% by weight of m-isopropylbiphenyl, from 40 to 75% by weight of p-isopropylbiphenyl and from 5 to 40% by weight of diisopropyldiphenyl, and a pressure-sensitive recording paper sheet comprising a colour-development sheet coated with microcapsules containing a dye solution which is composed of the chromogenic dye-precursor material and the substantially odorless solvent, and a colour-developer sheet.

A dynamic type memory device includes a plurality of one-transistor/one-capacitor type memory cells which are arranged in a matrix, first bit lines connected to the memory cells, second bit lines, and first capacitors respectively connected to the second bit lines and having a capacitance equal to 1/2 of that of the memory cell capacitor. This memory device further has second capacitors respectively connected to the second bit lines and having a capacitance equal to 1/2 of that of the memory cell capacitor, first switching transistors connected respectively between a power source terminal and the first capacitors, and second switching transistors connected respectively between a ground terminal and the second capacitors.

Growing community of inventors

Iwaki, Japan

Yoshio Okada