Tokyo Shibaura Electric Co., Ltd.

Tokyo Shibaura Denki Kabushiki Kaisha

Agency of Industrial Science and Technology

Nippon Hoso' Kyokai

Vlsi Technology Research Association

Yoshio Nishi

Satoshi Shinozaki

Yukuya Tokumaru

Masanori Nakai

Shintaro Ito

Junichi Nakamura

Hiroshi Iwai

Hideharu Egawa

Kenji Maeguchi

Norio Endo

Yoshihisa Mizutani

Norikazu Sawazaki

Soichi Iwamura

Yasuaki Nishida

Masaharu Watanabe

Masami Konaka

Toshimi Yamato

A method for manufacturing a semiconductor device that includes p- and n-type regions formed on an insulating substrate, and an interconnection layer electrically coupled with these p- and n-type regions. The interconnection layer is an n-type polycrystalline silicon layer which is electrically coupled with the p- and n-type regions through a metal silicide film formed between the interconnection layer and the p- and n-type regions.

Semiconductor device having a metal silicide layer connecting two

An MOS semiconductor device, wherein a buried region of silicon oxide or silicon nitride extends partly over the bottom plane of the channel region of an MOS transistor.

MOS Semiconductor device and method of manufacturing the same

A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and an n-type interconnection layer formed to be electrically coupled with said n-type semiconductor layer. The n-type interconnection layer is formed in contact with the p-type semiconductor layer and is set at such a potential as to apply a reverse voltage across the p-n junction between the n-type interconnection layer and p-type semiconductor layer, so as to electrically isolate the n-type interconnection layer from the p-type semiconductor layer.

Semiconductor device having contacting but electrically isolated

The integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on the N type semiconductor substrate, a first N type region extending through the P type semiconductor layer to reach the N type semiconductor substrate, a P type region formed in the first N type region and having a periphery along the outer periphery of the first N type region and a second N type region formed in the P type semiconductor layer. The integrated injection logic semiconductor device is constituted by a PNP lateral transistor utilizing the P type region, the first N type region and the P type semiconductor layer as the emitter, base and collector electrodes respectively, and a NPN vertical transistor utilizing the N type semiconductor substrate, P type semiconductor layer and the second N type region as the emitter, base and collector electrodes, respectively.

Integrated injection logic semiconductor devices

An information recording medium comprises a silicon substrate, a silicon dioxide film formed on one principal surface of the semiconductor substrate and a silicon nitride film formed on the silicon dioxide film. A recording electrode stylus is moved relative to and along the surface of the silicon nitride film while applying a recording signal voltage between the stylus and substrate, thus causing charges corresponding to the recording signal voltage to be passed through the silicon dioxide film by the tunnel effect and stored in the silicon nitride film.

Information recording medium and recording and reproducing system using

A method of manufacturing semiconductor devices is disclosed which comprises the steps of: forming at least one groove at a given location of a semiconductor substrate; laying an insulating film over the entire surface of the semiconductor substrate including the groove; depositing conductive material on the insulating layer to a thickness greater than half the width of an opening of the groove; and forming a MOS capacitor electrode of the conductor layer left in the groove by etching the deposited conductor layer until the insulating film other than its portion within the groove is exposed.

Method of manufacturing semiconductor devices

A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.

Method of manufacturing intergrated injection logic semiconductor

Method of manufacturing integrated injection logic semiconductor devices

An integrated injection logic semiconductor device is composed of an N type semiconductor substrate, a P type layer, a first N type region so formed as to penetrate through the P type semiconductor layer and contact the N type semiconductor substrate, a second N type region formed in the P type semiconductor layer, and a P type region formed in the first N type region. A third N type region is provided surrounding said first and second N type regions and penetrating through the P type semiconductor layer. I.sup.2 L circuit is composed of a lateral PNP transistor whose emitter, base and collector are constituted by said P type region, said first N type region and said P type semiconductor layer, respectively, and a vertical NPN transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, said P type semiconductor layer and said second N type region, respectively.

Integrated injection logic with both grid and internal double-diffused

A field effect transistor includes a thin silicon layer formed on a sapphire substrate and having source, gate and drain regions. A buried layer of the same conductivity type as that of the gate region and a higher impurity concentration than that of the gate region at the lower portion of a junction between the source and gate regions.

Field effect transistors

A semiconductor device comprises a D.C. voltage supply region comprising a semiconductor substrate of one conductivity type having a first layer of high impurity concentration at least at its surface, and a second layer of low impurity concentration and of the same conductivity type as that of the D.C. voltage supply region, provided thereon and formed interiorly with a thin buried layer of the opposite conductivity type to that of the second layer at the vicinity of the D.C. voltage supply region. A grounding region of said opposite conductivity layer is provided in a manner to surround a specified region of the second layer and extend from the surface of the second layer to the buried layer, said surrounded specified region serving as a signal input region. In the surface of the signal input region, there is provided at least one signal output region constituting a diode together with the signal input region.

Semiconductor device

An integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on said semiconductor substrate, and N type first region formed in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in said first N type region, a second N type regionformed in said P type semiconductor layer, and a second P type region formed between said second N type region and said N type semiconductor substrate in a manner connected directly to said N type semiconductor substrate. An integrated injection logic circuit is comprised of a lateral NPN transistor whose emitter, base and collector are constituted by said first P type region, first N type region and P type semiconductor layer, respectively, and a vertical PNP transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, P type semiconductor layer plus second P type region, and second N type region, respectively.

I.I.L. with graded base inversely operated transistor

A P type semiconductor layer is formed on an N type semiconductor layer by vapour epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.

An integrated injection logic semiconductor device which comprises an N type semiconductor substrate; a P type semiconductor layer superposed on the N type semiconductor substrate; a first N type region formed in the P type semiconductor layer; a second N type region formed in the P type semiconductor layer; and a P type region formed in the first N type region, wherein the first N type region is connected to the N type semiconductor substrate through an N type connector region formed between the first N type region and N type semiconductor substrate.

I.I.L. with region connecting base of double diffused injector to

A non-volatile semiconductor memory device includes source and drain regions formed on a semiconductor substrate to define p-n junctions with the substrate and a gate layer having a silicon oxide film and a silicon nitride film. A high impurity concentration diffusion layers are formed around at least one of the source and drain regions, which have the same conductivity type as the substrate, an impurity concentration of above 10.sup.17 atoms cm.sup.-.sup.3 and a width of below 1 .mu.m.

Growing community of inventors

Yokohama, Japan

Yoshio Nishi