Matsushita Electric Industrial Co., Ltd.

Yoshio Nirasawa

Norihide Kinugasa

Hideo Hamaguchi

Sachi Ota

Yuji Amano

A display panel control circuit includes a voltage controlled oscillator (VCO) for outputting a clock signal, a first-panel horizontal system pulse generation section, a second-panel horizontal system pulse generation section, a vertical system pulse generation section which is commonly used among the first and second panels, a phase comparator, and a smoothing element. The first-panel horizontal system pulse generation section and the second-panel horizontal system pulse generation section respectively generate a reference signal of a first-panel horizontal system output group and a reference signal of a second-panel horizontal system output group from signal VCOCLKoutput from the VCO. Thus, it is possible to simultaneously drive two different panels.

Control circuit for displaying the same video simultaneously to two or more panels

A power-on reset circuit of the present invention comprises: a first p-channel MOS transistor having the gate and the drain which are grounded and having a substrate which is connected to a power supply; a first resistor which is inserted and connected between the above-mentioned power supply and the source of the above-mentioned first p-channel MOS transistor; a first inverter having an input terminal which is connected to the source of the first p-channel MOS transistor; and a power-on reset signal output terminal which is connected to an output terminal of the first inverter.

Power-on reset circuit

An influence of a switching noise caused by a horizontal shift clock to an oscillation frequency of a voltage controlled oscillator should be eliminated, to prevent an image shift in a PAL skip period. For this purpose, an odd number line horizontal shift clock from an odd number line horizontal shift clock generator and an even number line horizontal shift clock from an even number line horizontal shift clock generator are switched by a horizontal shift clock switching circuit, to be input to a color LCD panel. The horizontal shift clock switching circuit selects and outputs either the odd number line horizontal shift clock or the even number line horizontal shift clock according to a line identifying signal, in a normal period. By contrast, in a PAL skip period a selecting state of the shift clock is inverted immediately upon start of a PAL skip period, from a selecting state right before the start of the skip period, and the selecting state is again inverted in half a cycle of a horizontal scanning period.

Horizontal shift clock pulse selecting circuit for driving a color LCD panel

An output circuit may include a power supply terminal, a ground terminal, and an output terminal connected to a capacitive load. Depending on the state of a load control input signal, the output circuit performs selectively a charging-current supplying operation of supplying a charging-current from the power supply terminal to the capacitive load and a discharging-current withdrawing operation of withdrawing a discharging-current from the capacitive load to the ground terminal. An overcharging-current prevention switch is provided to detect a short circuit between the output terminal and the ground terminal so as to stop or suppress the charging-current supplying operation. An overdischarging-current prevention switch is provided to detect a short circuit between the output terminal and the power supply terminal so as to stop or suppress the discharging-current withdrawing operation.

Capacitive load driving circuit and liquid crystal display

A PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal is provided. The PLL circuit has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.

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Muko, Japan

Yoshio Nirasawa