Hitachi, Ltd.

Yoshio Miki

Tatsuya Kawashimo

Akihiro Takamura

Takeshi Kato

Tatsuya Saito

Tadakatsu Nakajima

Makoto Hanawa

Jun Okitsu

Hiroaki Fujii

Yoko Shiga

Kentaro Shimada

Kei Suzuki

Masahiro Kato

Noboru Masuda

Yonetaro Totsuka

Shun Kawabe

Yoshio Takamine

Yasuhide Mori

Total power consumption of information-processing devices and power supply/cooling facilities is reduced to realize energy saving operation of information-processing system. The information-processing system includes information-processing devices, power supply facilities, cooling facilities and an operations management device. The operations management device is connected to the devices and the facilities and includes layout information constituted of locations and operating information of the devices and locations and environmental information of the facilities. Also, the operations management device obtains the power consumption of the devices, the power supply loss of the power supply facilities and the cooling power of the cooling facilities by using the layout information, and then allocates the workloads to the devices so as to reduce the total sum of power consumption, supply loss and cooling power.

Operations management methods and devices thereof in systems

Operations management methods and devices thereof in information-processing systems

Provided is an information recommendation system capable of recommending an unexpected item which a user is interested in but cannot assume easily. A server gives one or more times of initial recommendations of recommending information by a means of a user profile and a behavior history, and narrows down second recommended items to recommend next by using not only information relating to items having responses but also information relating to items having no response together. In narrowing down, the items are arranged by means of an item arrangement program by using the results of the initial recommendations, and it is identified depending on similarity by means of a boundary calculation program where the boundary between user's interest and no interest is positioned in all the items. Then, it is identified where items not recommended yet are positioned in user's interest/no interest the areas, and items in the vicinity of the boundary between the interest and no interest are determined as the second recommended items which are not uninterested and maximize unexpectedness.

Method of recommending information, system thereof, and server

A construction of the present invention includes a procedure of setting in advance a storing area in a converted instruction storing area table for recording a corresponding relation between a program before conversion and a storing address of a converted program at an initialization processing portion of an emulation program. In setting the storing area, address information on a memory on a portion whose execution frequency is high upon an emulation operation is acquired, and an address that brings about cache conflict on an instruction cache with the portion whose execution frequency is high is excepted and set as an area to store therein a converted instruction.

Memory management method for dynamic conversion type emulator

A hierarchical server system efficiently balances the processing load thereon and for shortening the processing time therein is provided, such as a web server system. A system controller, a load balancing device, and a shared memory are provided in a multi-layer server system made of a plurality of servers. When processing implemented with a first layer server is temporarily stopped in order to acquire information needed for processing from a second layer server, process information needed to resume the processing is recorded in the shared memory. When the necessary information is sent back to the first layer server, the system controller inquires about work statuses of all first layer servers to select another first layer server to resume the processing based upon the inquiry results. The then selected first layer server then resumes the processing using the information that was sent back and the process information in the shared memory.

Hierarchical server system

A main logical unit and a standby logical unit are defined by a process controller in a shared main memory multiprocessor, and an information storage space accessible from both logical units is provided. The main logical unit stores address information onto that information storage space by indicating a memory area it controls as the main memory area. When failover or cloning becomes necessary, the standby logical unit searches the information on the applicable address. Then from the applicable information, it also searches information on the main memory area controlled by the main logical unit to establish in itself and forms a processing environment and state identical to the main logical unit such that the standby logical unit takes over all or a portion of the processing of the main logical unit. This enables the construction of a server system of high operability to overcome failures and poor response times by failover and cloning, etc.

Server system operation control method

Information processor

A branch prediction apparatus to minimize branch penalties in pipeline or concurrent processing of a sequence of instructions correctly predicts a pattern in which &ldquo;branch taken&rdquo; and &ldquo;branch not taken&rdquo; alternately appear. The apparatus includes a branch prediction table to keep one history bit and a 2-bit counter for each branch instruction, a prediction generator to output a value of the history bit when the counter has a value of 0 or 2 and to output a value obtained by reversing the history bit when the counter has a value of 1 or 3, and a counter controller which compares a result of branch with a value of the history bit. The counter controller sets 0 to the counter value when the result matches the value and adds one to the counter value when the result does not match the value and the counter value is other than 3.

Branch prediction apparatus

In the transmission of a logic signal, there is a reduced maximum value and a reduced average value of the number of bits varied by transforming an input level representation original logic signal having n bits into a transition representation logic signal of m groups with only a maximum of k bits varied, wherein k and m are integer numbers, n is greater than k and each value of k and m is greater than 1. The transformed logic signal of m groups is transmitted. The transmitted logic signal of m groups is then transformed into the original logic signal having n bits. A maximum number of bits varied is k, which can be below n/2 as a maximum, which is less than an average bit variation of the input original signal.

Logic circuit and signal transmission method

A logic circuit for use as a selector having multiple inputs and high operation speed. The logic circuit includes a first FET having a first electrode connected to a first power supply, a second electrode connected to an output terminal and a third electrode connected to an intermediate control node, and a plurality of logic blocks parallelly connected between the second power supply and the output terminal. Each logic block includes second and third FETs being of a conductivity type opposite to that of the first FET and connected in series between the output terminal and a second power supply. Each logic block also includes a fourth FET being of the same conductivity type as the second and third FETs and having a third electrode connected to the third electrode of the second FET, a first electrode connected to the third electrode of the third FET and a second electrode connected to the intermediate control node. The conduction resistance between the output terminal and the first power supply is reduced and the parasitic capacitance added to the output terminal is also reduced, thereby allowing the logic circuit to be operated at high speed.

Logic circuit

A method of effecting a branch operation without the need of instruction fetching is carried out according to the taken/untaken branch with respect to a program containing plural branch instructions, and the method is performed by an apparatus information processing. By detecting a branch instruction stored in an instruction buffer, determining its branch distance and branch condition, and if the branch distance is less than a predetermined positive distance, by then providing that branch condition as an execution condition for the instruction located within said predetermined distance to store in an instruction register, a series of instructions succeeding that branch instruction can be processed into a conditional instruction in the apparatus. The instructions may be continuously executed without refetching instructions, in both cases that a branch condition is taken and untaken. Also, the penalty of miss-prediction of a branch will be minimized.

Branch operation system where instructions are queued until preparations

Soft errors generated at an active time are reduced by adding a small-scale circuit to a high performance LSI, such as a processor without reducing the performance of the circuit. The processor has individual logic circuits each having a plurality of stages of logic gates for outputting true signals and complement signals for the individual logic gates. A latch circuit latches the true and complement signals of the logic circuits separately and a compare circuit detects for an error by comparing the true and complement output signals of the logic circuits to determine if they are at the same logical signal level or not, just upstream of the latch in which the individual true and complement output signals of the final logic circuit stages are individually latched. When the compare circuit detects an error because the true and complement output signals are at the same logical signal level, a recovery process is executed.

Logic circuit having error detection function and processor including

A wiring route is determined between terminals on an integrated circuit on the basis of information concerning the terminals and areas of the integrated circuit through which a wire can be routed. A mesh memory holds information of mesh points of a wiring area partitioned in a mesh-like pattern. A wavefront memory holds information concerning mesh points constituting the leads of searching point arrays. An expansion point extracting unit selects a source point from the mesh points for a succeeding search from the leading mesh points on the basis of costs. Addresses and costs for mesh points neighboring the source point are calculated. A searching point register holds information concerning the mesh points obtained through the calculation. A determination is made of whether or not the mesh points placed in the searching point register can be searched, and if so they are written to the mesh memory. Duplicate information stored in the searching point register is eliminated. It is then determined whether or not the mesh points corresponding to the terminals to be wired are contained in the searching point register. If so, the wiring route is determined and the process concluded.

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Kodaira, Japan

Yoshio Miki