Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Amkor Technology Singapore Holding Pte. Ltd.

Yoshio Matsuda

Kazuyasu Fujishima

Kazutami Arimoto

Hideto Hidaka

Masaki Tsukude

Tsukasa Ooishi

Kiyohiro Furutani

Koichiro Mashiko

Noriaki Matsumoto

Mikio Asakura

Masahiro Shimizu

Akihiro Goto

Katsuhiro Tsukamoto

Harufusa Kondoh

Hiromi Notani

Isamu Hayashi

Kazuaki Tajima

Masahito Sato

Takahumi Miyamoto

Katsumi Dosaka

Hideshi Miyatake

Koji Bando

Hironori Matsushima

Shaun Bowers

Pedro Joel Rivera-Marty

Takashi Arita

Takao Takahashi

Akinobu Kawazu

Tsukasa Oishi

Hiroshige Ogawa

Koichi Minami

In one example, an electronic device comprises a substrate structure, comprising a base comprising a top side and a bottom side, a first lead, and a flag comprising a top side, a bottom side, and a flag lead. The electronic device also comprises an electronic component comprising a top side and a bottom side, a first electrode at the bottom side of the electronic component, and second electrode at the top side of the electronic component, an encapsulant contacting a lateral side of the electronic component and a lateral side of the base, and a first interconnect in the encapsulant, coupled between the first electrode and the first lead. The second electrode is coupled with the flag lead via the base. Other examples and related methods are also disclosed herein.

Electronic devices and methods of manufacturing electronic devices

In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.

Content addressable memory device having match line equalizer circuit

A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation in bond wire connection terminal positions of the interposer, and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the fluctuation in the arrangement position of the semiconductor chip on the interposer and the fluctuation in the bond wire connection terminal positions of the interposer.

Wiring design support apparatus for bond wire of semiconductor devices

A design support apparatus, when designing multichip packages, verifies connections between a semiconductor chip and leads of a lead frame. Distances between two wires or distances between the wires and the other components are calculated using three-dimensional drawing data (CAD data) and semiconductor package data. Components of the semiconductor packages such as wires, lead frames, or die pads are drawn in the three-dimensional drawing data. The semiconductor package data describes specifications of the semiconductor packages such as outer sizes of the packages. Distance values are compared with design rule data. The design rule data defines constraints on the positional relationship between each wire and each component. The design support apparatus determines whether the acquired positional relationship is proper on the basis of design rule data.

Design support apparatus and method for designing semiconductor packages

A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

Semiconductor memory device for simple cache system

A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

Semiconductor memory device with redundancy circuit

Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

Semiconductor memory device and data transferring structure and method

A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

Random access memory with a plurality amplifier groups for reading and

A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers. More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

Bit line structure for semiconductor memory device

A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.

Semiconductor memory device having an SRAM as a cache memory integrated

A method for manufacturing a curved surface multi-layer wiring board having the through-holes and high accurate inner patters with a high reliability. A curved surface multi-layer wiring board is manufactured by processes for forming the inner pattern on the copper clad substrates, and for perforating the holes to the substrates and prepregs, and for laying-up these substrates and prepregs, then for pressing these substrates and prepregs in the formation mould. Then the outer pattern are formed by the laser exposure process after the through holes are connected between the layers. A method is also provided for repeating the laying-up processes in order to obtain a curved surface multi-layer wiring board of which is a three dimensional curved surface.

Method for manufacturing a curved surface multi-layer wiring board

Growing community of inventors

Hyogo, Japan

Yoshio Matsuda