Hitachi, Ltd.

Hitachi Computer Electronics Co., Ltd.

Yoshio Kiriu

Hiroshi Kosuge

Ryoichi Kurihara

Hitoshi Abe

Yasuhiko Hatakeyama

Toshimitsu Ando

Shigeko Yazawa

Eiji Fujiwara

Junichi Taguri

Sigeru Kaneko

Kazuya Iwasaki

Shigeru Kaneko

An error detecting and correcting apparatus includes a unit for receiving an encoded word including a plurality of b-bit bytes (b is an integer not less than two) and generating syndrome from the encoded word according to a first parity check matrix H.sub.1, and a unit for correcting errors in the received encoded word based on the syndrome.

Error detecting and correcting method and system

An extended, hierarchical storage system includes a main storage, an extended storage, and a work storage having a speed and capacity intermediate therebetween. Additionally, a relatively small, high-speed buffer storage is provided as an adjunct to a processor. The work storage implements a store-in mode and incorporates a flag representative of validity of data therein, which, in turn, impacts upon whether an update to lower ranking memory is necessary upon removal of data stored therein.

Multiple rank hierarchical data storage system with data coherence

Memory expansion using memory packages of different generations is performed without unnecessarily increasing the minimum memory capacity of a memory device and while obtaining a high error detecting ability and high reliability. In expanding the capacity of a memory device by using first generation 1M.times.1 bit IC memory packages, second generation 4M.times.4 bits IC memory packages, or third generation 16M.times.8 bits IC memory packages, the total code length is set to 40 bits, a 4's multiple, within a range longer than the total code length necessary for S4ED and shorter than the total code length necessary for S8ED, and a reduced code is used for enhancing the S8ED function. In this manner, wasteful first generation IC memory packages can be reduced in number, and the error detecting ability of a memory device using third generation memory packages can be retained substantially the same as that of a memory device using first generation memory packages.

Data error correcting/detecting system and apparatus compatible with

Frames of digital data each representing a single picture of a video motion picture display are handled in a computer system with an extended memory operating in parallel with a computer system instruction processor and main memory to bypass the computer system input/output processor for continuously outputting the video information on a real time basis. The outputted data may be recorded continuously at a constant data rate for an entire motion picture worth of information or actually displayed on the video display on a real time basis. The extended storage has a memory larger than the main memory, where all of the frame data is stored and read out in high speed bursts to a buffer that continuously reads the data out of the buffer for outputting. At least a start command and a starting address in the extended memory are contained within the main memory to be read out and decoded by the instruction processor and computer system memory storage control, for transfer to the extended memory, where they are used to start the program, which includes extended memory control words stored in the main memory, which control words are decoded and executed in the extended memory in parallel with the computer system instruction processor. Addresses of succeeding frames are generated and decoded and used for fetching entirely within the extended memory, for memory areas according to indirect addressing. The extended memory has external data transfer and internal data transfer registers that hold command words for respective transferring programs that may be operated in parallel, with conflict between external transfer and internal transfer being decided in favor of external transfer to assure continuous data outputting.

Information processing system

An extended, hierarchical storage system includes a main storage, an extended storage, and a work storage having a speed and capacity intermediate therebetween, Additionally, a relatively small, high-speed buffer storage is provided as an adjunct to a processor. The work storage implements a store-in mode and incorporates a flag representative of validity of data therein, which, in turn, impacts upon whether an update to lower ranking memory is necessary upon removal of data stored therein.

An error detecting apparatus in which an error within an arbitrary and continuous (b-1) bit block is detected using a SEC-DED-SbED code. The (b-1) bit block is any continuous (b-1) bit block within an information consisting of several b bit blocks. The data are encoded by using a power of a matrix C, defined as: ##EQU1## and a matrix B. Matrix B is comprised by arbitrarily replacing the rows and columns of the power of C matrix with row vectors from a set of (b+1) vectors: ##EQU2## The partial matrices obtained from matrices B and C are used to construct a parity matrix. Syndromes are computed from the information and the party matrix to detect errors.

Error detection system

An apparatus for controlling a data transfer between storages in an information processing system having a main storage, an extended storage, and a processor in which data is transferred between the main storage and the extended storage by use of a synchronous instruction and an asynchronous instruction. The apparatus includes a unit to hold data transfer control information specified by the asynchronous instruction and a unit to hold data transfer control information specified by the synchronous instruction. Depending on a synchronous instruction or an asynchronous instruction, the data transfer is controlled to be achieved according to data transfer control information held in the unit associated with the instruction. The content of the unit is updated depending on the amount of data to be transferred. When a request of a data transfer is made by a synchronous instruction during a data transfer caused by an asynchronous instruction, the data transfer of the asynchronous instruction is interrupted to control the data transfer of the synchronous instruction to be executed. When the data transfer is completed, based on the content of the unit to hold data transfer control information of the asynchronous instruction, the data transfer of the asynchronous instruction interrupted is resumed.

Apparatus for controlling data transfer between storages

A data transmission control device for controlling the data transfer between two memory means on the basis of an instruction from a processor is disclosed in which the instruction from the processor is decoded, a transfer request is issued to each memory means a plurality of times, depending upon a transfer unit indicated by the decoded instruction and an access unit of each memory means, a data buffer is provided between the memory means to temporarily store data whichis transferred from one of the memory means to the other memory means, and the issue of a transfer request to each memory means is allowed or stopped in accordance with the quantity of data stored in the data buffer.

Data transmission control device for controlling transfer of large

A method for correcting and detecting errors using the SEC-DED-SbED code is provided, wherein the information consisting of several blocks of b bits is encoded based on the parity matrix including any of b.times.b matrix X q (q=1 to b) in which each row of b.times.b matrix ##EQU1## is cyclically displaced along the column direction by a desired number (q) of bits in each partial matrix corresponding to the above block.

Method for correcting and detecting errors

An access request selecting circuit for selectively accepting access request signals produced from a plurality of access request sources. Different series of recurrent time intervals are assigned to the access request sources. When a memory request signal is supplied from an access request source in a series of recurrent time intervals which are assigned to the access request source such a memory request signal is accepted. At this time, if an attendant signal produced in association with the memory request signal is supplied, this attendant signal is also accepted.

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Hadano, Japan

Yoshio Kiriu