Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Koki Co., Ltd.

Hirose Electric Company, Ltd.

Yoshio Kawamura

Shigeo Moriyama

Fumihiko Uchida

Natsuki Yokoyama

Yoshifumi Kawamoto

Kazuo Sato

Eiichi Murakami

Kenichi Mizuishi

Kan Yasui

Tsuneo Terasawa

Souichi Katagiri

Toshiei Kurosaki

Shinji Tanaka

Sumio Hosaka

Shinji Kuniyoshi

Akihiro Takanashi

Ui Yamaguchi

Hiroyuki Kohida

Masahiko Sato

Masayuki Nagasawa

Sadayuki Nishimura

Ryousei Kawai

Masatoshi Sakurano

Yoshinori Nakayama

Hideo Kashima

Akira Koide

Tatsuo Harada

Eiichi Seya

Tatuharu Yamamoto

Yasuaki Horiuchi

Mitsuhiro Shikida

Toshimitsu Miyada

Kensaku Sato

Yoshio Homma

Kunio Harada

Shinji Okazaki

Seiichi Kondo

Kenko Uchida

Norio Saitou

Kimiaki Ando

Takeshi Furusawa

Kikuo Kusukawa

Yosuke Seo

Mitsuo Ooyama

Minoru Hidaka

Youichi Kawakubo

Miyako Matsui

Shingo Ogawa

Yoshihisa Hosoe

Hitoshi Miyahira

Kahoru Takahashi

Yoshu Yoshiba

Hisashi Tsuruoka

Masamoto Akeyama

Satoshi Osabe

Jiro Kikuchi

Seiya Hashimoto

Yataro Kondo

Hirosi Kaida

Yoshizi Itoh

Takanori Simura

A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.

Fabrication system and fabrication method

A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.

Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system. Moreover, since the fabricating system including processing apparatuses is periodically controlled at a cycle time T min, the scheduling of a plurality of works can be made easy, to enhance the level of optimization, thus improving the productivity.

In a production process of a semiconductor device, planarizing of a wafer surface pattern can be performed to attain high planarity, good uniformity in the removal amount and improved controllability. This process include a step of planarizing a semiconductor wafer, from which at least two different films have been exposed, by polishing with a grindstone and a dispersant-containing processing liquid.

Planarizing method of semiconductor wafer and apparatus thereof

A method of manufacturing is described wherein a semiconductor device has a substrate as workpiece with an insulation film formed on the substrate, openings formed inside the insulation film, a first conductive film is formed inside the openings and on a surface of the insulation film, a second conductive film is formed on the first conductive film, and the first and the second conductive films are formed inside openings by planarizing a surface of second conductive film and a surface part of the first conductive film with a fixed abrasive tool. The method includes supplying a first processing liquid, planarizing the surface of the second conductive film with the first processing liquid and the fixed abrasive tool, switching the supply of liquid from a first processing liquid to a second processing liquid, and planarizing the surface of second conductive film and the surface of part of the first conductive film with the second processing liquid and the fixed abrasive tool.

Method of polishing a semiconductor device

A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

Semiconductor device fabricating method

The problem of non-uniform polishing properties of a circumferential surface area of a substrate, so-called edge sagging phenomenon, is solved. When a thin film formed on a top surface of the substrate is polished while holding a back surface of the substrate, local stress at a circumferential end of the substrate is reduced by a guide installed so as to surround the substrate. Also, a deformation of the outer circumferential end portion of the substrate is reduced by a recessed groove provided on the guide. Since a thin film formed on the surface can be polished to be flat throughout the surface of the substrate without an occurrence of non-uniform polishing properties of the outer circumferential surface area of the substrate, so-called edge sagging phenomenon, a high-performance semiconductor device can be manufactured at a high yield and low costs.

Method for polishing surface of semiconductor device substrate

A method for fabricating a semiconductor device includes grindstone surface activation treatment by means of a brush or ultrasonic wave carried out when a concave/convex pattern of a semiconductor wafer is planarized by polishing a semiconductor wafer held by a wafer holder by using a grindstone constituted of abrasive grains and material for holding the abrasive grains onto which the semiconductor wafer is pressed with relative motion. The semiconductor wafer is processed with high removal rate and the polishing thickness is controlled accurately.

Method for fabricating semiconductor device and processing apparatus for processing semiconductor device

A processing method capable of presenting the processing condition with a high accuracy to improve the productivity, including a step of applying a first processing to a first substrate and a step of applying a second processing to the first substrate or the second processing to a second substrate and determining a correlation function for each of in-plane positions as the data for the difference in a plurality of processing steps to each of the in-plane positions in view of on the in-plain distribution data to the in-plane position of each of the substrate as a result of the plurality of processings, calculating the in-plain distribution characteristics of the substrate under a desired processing condition in view of the correlation function and processing the substrate based on the in-plain distribution characteristics.

Processing method, measuring method and producing method of semiconductor devices

The invention provides a process apparatus including a wafer holder, and a process method, in which high planarization performance, scratch free process, narrow edge exclusion and high uniformity can be maintained for more than 10,000 processed wafers. The invention is achieved by providing a unit for keeping a retainer and surface of a polishing wheel non-contact with each other and controlling the gap within a certain range and by setting compression strength of the retainer at more than 3,000 kg/cm .

Method and apparatus for planarizing semiconductor device

In order to manufacture a semiconductor device of high performance a small-sized transfer arm mechanism, capable of retaining a predetermined transfer stroke, is put to practical use without any increase in the height of the arm mechanism. The transfer arm includes arcuate portions having center axes different from each other, and restraint generating means for generating restraints in directions where the individual center axes are attracted. This way, a plurality of arms are joined by joints having a structure for transmitting rolling motions to the arcuate portions contacting each other to thereby control the drive shaft of the arcuate portions rotationally and thereby move the arms. This transfer arm mechanism is used in various environments including semiconductor manufacturing, such as DRAMs.

Semiconductor manufacturing apparatus for transferring articles with a

Method and apparatus for fabricating semiconductor devices

Growing community of inventors

Kokubunji, Japan

Yoshio Kawamura