Fujitsu Corporation

Fujitsu Semiconductor Limited

Yoshio Kajii

Toru Osajima

Takashi Ohkawa

Tsuyoshi Yanai

A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.

Semiconductor memory device

A base cell is configured such that P-type regionstoare arrayed in a column direction in an N-type well, N-type regionstoare arrayed in a column direction in a P-type wellnext to the N-type well, gate linesA andB passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regionsC andC are formed in the wellsandat outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Semiconductor integrated circuit having high-density base cell array

A base cell is configured such that P-type regions to are arrayed in a column direction in an N-type well , N-type regions to are arrayed in a column direction in a P-type well next to the N-type well, gate lines A and B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions C and C are formed in the wells and at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Growing community of inventors

Kawasaki, Japan

Yoshio Kajii