Fujitsu Corporation

Yoshio Hirose

Goji Nakagawa

Kyosuke Sone

Hiroyuki Utsumi

Takeshi Hoshida

Miyoshi Saito

Takumi Kishino

Hiroshi Okano

Yasutomo Sakurai

Koichi Odahara

Takumi Takeno

Toshiaki Saruwatari

Toru Watabe

Shinya Katoh

Takato Noda

Kazuhiro Nonomura

Hisao Nakashima

Shinji Sato

Yuichi Akiyama

Setsuo Yoshida

Koichi Yamashita

Hideo Miyake

Atsuhiro Suga

Shigetoshi Wakayama

Tomofumi Oyama

Yi Ge

Hideyuki Iino

Yasuki Nakamura

Yoshitaka Nomura

Teruhiko Kamigata

Takeshi Sasaki

Hitoshi Yoda

Shigeki Kawahara

Ken Ryu

Ataru Kumagai

Wouter Couzijn

An optical transmission apparatus includes a wavelength variable filter whose transmission light wavelength is variable; a receiver that receives light, the light being sent from another optical transmission apparatus and passing through the wavelength variable filter; a transmitter that sends to the another optical transmission apparatus, a utilization permission request for a second wavelength corresponding to a first wavelength of the light received by the receiver, the transmitter sending the utilization permission request as light of the second wavelength and in a form of a tone signal of a predetermined frequency; and a controller that, when receiving from the another optical transmission apparatus, a utilization permission notification of the second wavelength for a sender of the utilization permission request, configures a wavelength of a main signal to the second wavelength, the main signal being sent from the transmitter to the another optical transmission apparatus.

Optical transmission apparatus, optical transmission system, and optical transmission method

A transmission device includes an interface configured to acquire, from a base band unit having a communication destination that is one of remote radio heads, communication destination information relating to the remote radio head of the communication destination, a receiver configured to receive signals of given wavelength from optical termination devices, and a transmitter configured to transmit a first signal that includes wavelength information indicative of the given wavelength and the communication destination information to optical termination devices, wherein, when the receiver receives, from an optical termination device of the remote radio head of the communication destination from among optical termination devices, a second signal of the given wavelength according to the first signal, the receiver sets, between the receiver and the optical termination device, a relay path that relays communication between the base band unit and the remote radio head of the communication destination.

Transmission device, optical termination device, transmission system, and transmission method

An optical terminal device includes: a relay processing circuitry relaying communication between first base stations, respectively connected to optical terminating devices at branch destinations of a transmission path, and a control device controlling the first base stations in accordance with information acquired from a second base station covering a cell overlapping cells of the first base stations; a detecting circuitry detecting a sleep control instruction, issued for one of the first base stations from the control device, from the communication being relayed by the relay processing circuitry; and a control circuitry performing control, via the transmission path, to cause the optical terminating device connected to the one of the first base stations to shift to an operating state or a sleep state, which consumes less power than the operating state, in response to detection of the sleep control instruction, the optical terminating device being one of the optical terminating devices.

Optical terminal device, optical terminating device, and communication control method

An optical transmitting apparatus includes a variable optical attenuator of a magneto-optical effect type disposed by spatial coupling between a light source and an optical fiber, the variable optical attenuator configured to attenuate light output from the light source and coupled to the optical fiber, according to an input driving voltage; a generator configured to generate the driving voltage of the variable optical attenuator based on information to be superimposed on the light by the variable optical attenuator, the generator inputting the generated driving voltage into the variable optical attenuator; and a controller configured to control a bias of the driving voltage generated by the generator, the controller controlling an amplitude of the driving voltage generated by the generator, based on data according to characteristics between the driving voltage and an attenuation amount of the light by the variable optical attenuator.

Optical transmitting apparatus and optical level control method

A signal processing device includes digital signal processing circuits. Each of the digital signal processing circuits includes: a regeneration circuit that regenerates a bit stream front an electric field information signal of an optical signal; an error correction circuit that corrects an error in the bit stream; an encoder circuit that generates an encoded bit stream from received data; and a generation circuit that generates an electric field information signal from the encoded bit stream. An electric field information signal or a bit stream is given from a regeneration circuit, an encoder circuit or a generation circuit in a first digital signal processing circuit to a second digital signal processing circuit. A regeneration circuit, an error correction circuit or a generation circuit in the second digital signal processing circuit processes the electric field information signal or the bit stream given from the first digital signal processing circuit.

Digital signal processing circuit and signal processing device that includes a plurality of digital signal processing circuits

An integrated circuit includes a processor. An arithmetic logic circuit group includes a plurality of operation units and a connection channel connecting the operation units in a reconfigurable manner. Parameter-based dedicated hardware can change a process specification thereof by parameter setting. An intermodule interface connects the processor, the arithmetic logic circuit group, and the parameter-based hardware to each other.

Reconfigurable integrated circuit, system development method and data processing method

The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes '0'. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

Bus control system for integrated circuit device with improved bus access efficiency

In a processor, an operating unit executes an instruction within an instruction set, and a second operating unit executes other custom instructions. The second operating unit consists of a plurality of AND circuits, OR circuits, adders, selectors, and multiplexers. The information about which circuit should be combined with which circuit when the instruction is input is held in advance as structure information in a configuration memory. One piece of structure information corresponds to one custom instruction. The second operating unit in an optimum circuit structure determined based on this structure information executes the instruction. With this arrangement, it is possible to increase the processing speed than when the operating unit executes the processing.

Information processing apparatus with configurable processor

A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.

Data transfer circuit between different clock regions

The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIS) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes '0'. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

An OR circuit () OR-operates an emulator reset signal () based on a reset instruction from an emulator () and an external reset signal () supplied from an external reset generation circuit. The OR operation result is distributed and supplied to a processor () and a companion chip () as a system reset signal (), thereby initializing both chips of the processor () and the companion chip () in accordance with the reset the emulator ().

Reset control system and method

In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.

Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory

A command fetch control section has an address selection function of selecting the start address of an initialization program stored in a local memory (RAM ) or an external memory (ROM ) connected through external buses and , based on an address selection signal MS externally given. When a processor in which one or both of the supplies of its internal clocks and have been stopped after the system wad powered on, is to be restarted, the processor can read out the initialization program necessary for its restarting operation from the high-speed RAM . Thus the restarting operation can be performed rapidly.

Data processing system for performing software initialization

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.

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Kawasaki, Japan

Yoshio Hirose