Sharp Kabushiki Kaisha Corporation

Fujitsu Corporation

Fujitsu Display Technologies Corporation

Yoshio Dejima

Kenji Okamoto

Kiyoshi Ozaki

Satoru Kawai

Jun Inoue

An active matrix substrate includes, in a peripheral region that is disposed around a display region, a connecting portion formation region in which a plurality of line connecting portions are arranged. Each line connecting portion includes: a lower connecting portion; an organic insulating layer disposed on the lower connecting portion so as to be in contact with the lower connecting portion, the organic insulating layer having at least one aperture through which a part of the lower connecting portion is exposed; and an upper connecting portion disposed on the organic insulating layer and in the at least one aperture, the upper connecting portion being directly in contact with the part of the lower connecting portion within the at least one aperture. The organic insulating layer extends into an adjoining region that adjoins the connecting portion formation region. In the adjoining region, the organic insulating layer has a plurality of dummy apertures that are disposed so as not to overlap the lower connecting portions when viewed from the normal direction of the substrate, each dummy aperture exposing a part of an underlying layer that is located on the substrate side of the lower connecting portion. The upper connecting portions are not provided in the plurality of dummy apertures.

Active matrix substrate

A stagger type thin film transistor substrate in which each of a source and a drain of a thin film transistor has a laminated structure including a silicon semiconductor layer, a silicon semiconductor layer containing impurities, and a metal layer formed in that order and in which a gate insulator of the thin film transistor is formed on the source and the drain. A pixel electrode is connected to the source via a contact hole made in the gate insulator on the source. Additionally, a gate electrode of the thin film transistor formed on the gate insulator has a laminated structure including two layers of different electrode materials. Finally, the pixel electrode connected to the source is made of an electrode material used in a lower layer of the gate electrode.

Thin film transistor substrate and method for fabricating the same

A stagger type TFT substrate and a fabrication method therefor in which the number of exposure processes is reduced. A resist pattern is formed in an area on the TFT substrate where a drain bus-line (DB) is to be formed and an area on the TFT substrate where a TFT is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the DB and a channel area for the TFT. In addition, a resist pattern is formed in an area where a gate bus-line (GB) is to be formed and an area where a pixel electrode is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the GB and the pixel electrode. The DB and the channel are formed by one half tone mask and the GB and the pixel electrode are formed by another half tone mask. As a result, the number of exposure processes necessary for fabricating a stagger type TFT substrate can be reduced.

Method for fabricating a thin film transistor using a half-tone mask

A repairable integrated thin film transistor matrix substrate includes an insulated substrate, and a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on the insulated substrate. Each of the accumulated capacitance bus lines extend parallel to and between a pair of the gate bus lines, and has a plurality of auxiliary capacitance electrodes which extend from it. A first insulated film is provided on the gate and accumulated capacitance bus lines and the auxiliary capacitance electrodes. A plurality of operating films are formed on the first insulated film, and on each of the operating films, a corresponding thin film transistors are provided. At least two of the thin film transistors are electrically connected to each of the gate bus lines. Also included is a plurality of parallel drain bus lines which are provided substantially perpendicular to the gate and the accumulated capacitance bus lines on the first insulated film. Each drain bus line electrically connects at least two of the thin film transistors. In addition, a second insulated film having an opening over each of the thin film transistors is provided on the thin film transistors and the drain bus lines. Further, a plurality of pixel electrodes are provided on the second insulated film, which pixel electrodes being electrically connected to a corresponding one of the transistors via the opening. At least one first portion of at least one of the gate and the drain bus lines overlaps with at least one second portion of at least one of the auxiliary capacitance and the pixel electrodes. A method for repairing the matrix substrate generally includes electrically connecting a conductor to either sides of a defect to act as a bypass.

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Kawasaki, Japan

Yoshio Dejima