Canon Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Hitachi, Ltd.

Yoshinori Watanabe

Hiroyuki Hara

Shinya Sonoda

Yasutsugu Saijo

Takayasu Sakurai

Toshikazu Yasue

Tetsuo Oura

Katsuhiro Seta

Yuuji Saeki

Shiro Oishi

A sheet material feeding apparatus includes a sheet stacking portion for stacking recording sheets; a feeding roller for feeding the recording sheets from the sheet stacking portion; separating means for separating the recording sheet fed out by the feeding roller; a holder for holding the separating means, the holder being rotatably supported on a main assembly of the apparatus; first urging means for urging the holder toward the feeding roller; a preliminary regulating member, rotatably supported on the holder, for regulating a gap relative to the feeding roller; second urging means for urging the preliminary regulating member toward the feeding roller; a first regulating member, supported by the holder, for regulating rotation of the preliminary regulating member relative to the holder; and a second regulating member, provided in the main assembly of apparatus, for regulating rotation of the preliminary regulating member relative to the main assembly of the apparatus.

Sheet feeding device and recording apparatus with separating means

Sheet feeding device and recording apparatus

Disclosed is a semiconductor integrated circuit of a bipolar CMOS gate array type having a plurality of basic cells arranged in a matrix. Each cell comprises MOS transistors as memory cells, a bipolar transistor, a resistance and bit lines, for transferring data stored in the memory cells to the outside. The semiconductor integrated circuit is characterized in that the basic cells are grouped into a plurality of blocks, the bipolar NPN transistor in each block is used as a driver for reading operations of the data stored in the memory cells in each block, and the bit line is kept at a logic state '0' before the reading operations for the memory cells.

ROM with Bi-CMOS gate arrays

A semiconductor memory circuit device having memory cells constructed on a BiCMOS gate array includes amplifying means constituted by a bipolar transistor connected to the output stage of each of memory cells arranged in a matrix form on a semiconductor substrate and formed in a gate array memory cell configuration by use of the Master slice approach. The amplifying means amplifies the potential level of readout data of the memory cell and output the same to an output line, thus enhancing the driving ability of the output line and reducing the whole readout time for reading out data from the memory circuit.

Semiconductor memory circuit device having memory cells constructed on a

In a semiconductor memory device of a divided bit line system, read signals from memory cell blocks are sense-amplified together by a single differential bit line sense amplifier. The bit line sense amplifier includes a plurality of first transistors, the base electrodes of which are connected to local bit lines of the memory cell blocks, the emitter electrodes of which are commonly connected to corresponding main bit lines, and the collector electrodes of which are connected to a first power supply node, a second transistor, which forms a differential pair with each of the first transistors, the base electrode of which is applied with a reference bias potential, and the emitter electrode of which is connected to the main bit lines, a current source connected between the emitter electrode of the second transistor, and a second power supply node, and a load circuit connected between the collector electrode of the second transistor and the first power supply node. The main bit lines with a heavy load can be driven by the emitters having a large driving force, and the outputs from the memory cell blocks can be sensed without going through selectors, thus attaining high-speed read access.

Semiconductor memory device

An ISDN communication controller or a multi-circuit communication controller is implemented in a sheet of communication adapter board. For each channel or circuit, a dedicated subprocessor section conducts communication processing. In each subprocessor section, a local bus is disposed to connect a CPU, a serial controller, and an RAM. In a main processor section controlling the subprocessors, a local bus is employed to connect a CPU, an RAM, and an ROM. In a system processor section exclusively achieving information processing, a system bus is used to connect a CPU and a main memory. The local buses are connected via respective controllers to an upper-level local bus. A shared RAM is connected via a controller to the upper-level local bus and the system bus. The controllers of the subprocessor sections translate addresses to be outputted from the main processor section to the upper-level local bus to supply translated addresses to the respective local bus.

Growing community of inventors

Yokohama, Japan

Yoshinori Watanabe