Fujitsu Corporation

Canon Kabushiki Kaisha

Yoshinori Tomita

Hiroshi Matsuda

Masahiro Haruta

Hirohide Munakata

Takashi Hamamoto

Yutaka Tamiya

Hidetoshi Matsuoka

Hiroyuki Higuchi

Toshiyuki Ichiba

An information processing device includes: a memory; a processor coupled to the memory and configured to: perform, based on input descriptions of a first circuit module that performs a first task and a second circuit module that receive data output from the first circuit module and performs a second task, high-level synthesis of the first circuit module and the second circuit module; synthesize an interface circuit that includes a memory that performs data transfer between the circuit modules based on write information of the data and read information of the data; calculate a minimum operation start interval of the interface circuit based on the write information of the data and the read information of the data; and provide, when the calculated minimum operation start interval is larger than a minimum operation start intervals of the first circuit module and the second circuit module, a storage element in the interface circuit.

Information processing device, information processing method, and recording medium

A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.

Debug circuit, semiconductor device, and debug method

A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.

Semiconductor memory of which defective cell is replaceable with redundant cell and manufacturing method of semiconductor memory

An optical recording medium and an optical recording process using such a medium are provided. The optical recording medium comprises a photo-polymerizable monomer having a hydrophilic group, a hydrophobic group, and at least one unsaturated bond in the molecule.

Optical recording medium and optical recording process using such medium

An optical recording medium and an optical recording process using such a medium are provided. The optical recording medium comprises a photopolymerizable monomer having a hydrophilic group, a hydrophobic group, and at least one unsaturated bond in the molecule.

Growing community of inventors

Yokohama, Japan

Yoshinori Tomita