Kabushiki Kaisha Toshiba

Yoshinori Takano

Toru Tanzawa

Shigeru Atsumi

Tadayuki Taura

Hitoshi Shiga

Akira Umezawa

Kentaro Watanabe

Yasuhiko Honda

Masao Kuriyama

A current difference divider circuit with a plurality of current sources is provided. The divider circuit includes a first current source which is operable to generate a first current, a second current source for generation of a second current less in magnitude than the first current, and a third current source for generating a difference current with its magnitude equivalent to a difference between the first and second currents and for generating a third current resulting from the division thereof. The circuit further includes a fourth current source for generating a fourth current obtainable by mirroring of the second current. The third and fourth currents are added together to provide a fifth current, which is then output.

Current difference divider circuit

A semiconductor memory device is provided using a sense amp circuitry capable of lowering a supply voltage. The semiconductor memory device includes an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from the array of memory cells with a reference voltage applied to a reference sense line to determine the data; and a reference voltage generator configured to generate the reference voltage applied to the reference sense line.

Semiconductor memory device and current mirror circuit

A semiconductor memory device is disclosed which includes an array of memory cells for storing data depending on whether current pull-in is present or absent or alternatively whether it is large or small, a plurality of sense lines with read data of the memory cell array transferred thereto, a reference sense line for common use in data sensing at the plurality of sense lines while being given a reference voltage for the data sense, and a sense amplifier array having a plurality of sense amplifiers for amplifying a difference voltage between the plurality of sense lines and the reference sense line to thereby determine read data.

Semiconductor memory device having plural sense amplifiers

A nonvolatile semiconductor memory device with a plurality of read modes switchably built therein is provided. This nonvolatile semiconductor memory device is the one that has a memory cell array in which electrically rewritable nonvolatile memory cells are laid out and a read circuit which performs data readout of the memory cell array. The nonvolatile semiconductor memory device has a first read mode and a second read mode. The first read mode is for reading data by means of parallel data transfer of the same bit number when sending data from the memory cell array through the read circuit up to more than one external terminal. The second read mode is for performing parallel data transfer of a greater bit number than that of the first read mode when sending data from the memory cell array to the read circuit while performing data transfer of a smaller bit number than the bit number when sending data from the read circuit up to the external terminal.

Nonvolatile semiconductor memory device with first and second read modes

A semiconductor integrated circuit device includes first to fourth bit lines and a redundant bit line, first to fourth column gate transistors and a redundant column gate transistor coupled to each of the first to fourth bit lines and the redundant bit lines, first to fourth column select lines and a redundant column select line coupled to each of the first to fourth column gate transistors and the redundant column gate transistor. The second column select line passes through the first bit line. The third column select line passes through the first and second bit lines. The fourth column select line passes through the first, second and third bit lines. The redundant column select line passes through the first, second, third and fourth bit lines.

Fast data readout semiconductor storage apparatus

A non-volatile semiconductor memory device includes: an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.

Non-volatile semiconductor memory device

The semiconductor memory comprises a reference current generator, first and second current converters, sense amplifiers for read, and sense amplifiers for verify. The reference current generator generates a first voltage dependent upon the current flowing through a reference cell. The first current converters, to which the first voltage is input, each generate a second voltage. The second current converters, to which the first voltage is input, each generate a third voltage. The sense amplifiers for read output data of a selection memory cell, comparing the voltage of the data-line for read with the second voltage. The sense amplifiers for verify output verify data of the selection memory cell, comparing the voltage of the data-lines for verify and the third voltage.

Nonvolatile semiconductor memory having page mode with a plurality of banks

Constant voltage generation circuit and semiconductor memory device

A semiconductor integrated circuit includes first to eighth column selection transistors and ninth to twelfth column selection transistors. The ninth column selection transistor is connected to the first and second column selection transistors. The tenth column selection transistor is connected to the third and fourth column selection transistors. The eleventh column selection transistor is connected to the fifth and sixth column selection transistors. The twelfth column selection transistor is connected to the seventh and eighth column selection transistors. A first column selection line is connected to gates of the first, third, fifth and seventh column selection transistors. A second column selection line is connected to gates of the second, fourth, sixth and eighth column selection transistors. Third to sixth column selection lines are connected to gates of the ninth to twelfth column selection transistors, respectively.

Semiconductor storage apparatus

A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.

There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

A memory cell is connected to a cell-based bit line. The cell-based bit line is connected to a bit line via a Y decoder. The bit line is connected to a sense bit line via a separation circuit. This sense bit line is connected to a sense line via a bias circuit. An amplifier circuit amplifies a signal voltage on the sense line together with a reference voltage for sensing data. The sense line is connected with a sense line initialization circuit for setting the sense line to a specified voltage. The bit line is connected with a bit line initialization circuit for setting the bit line to a specified voltage. Both the sense line initialization circuit and the bit line initialization circuit are activated in a given period before the amplifier circuit operates to sense data. Thus, the sense line and the bit line are set to specified voltages.

Nonvolatile semiconductor memory device with initialization circuit and control method thereof

A first level shifter outputs one of a first potential and a second potential lower than the first potential from an output terminal in accordance with the level of an input signal. A second level shifter outputs one of the first potential and a third potential lower than the second potential from an output terminal in accordance with the output potential from the first level shifter. A third level shifter outputs one of the first and second potentials from an output terminal in accordance with the level of the input signal. A first switching circuit selects the output voltage from the second level shifter when a high-speed operation is required such as in a read operation.

Growing community of inventors

Ichikawa, Japan

Yoshinori Takano