Kabushiki Kaisha Toshiba

Yoshinori Shigeta

Yasuro Shobatake

Toshiki Kizu

Takaya Ogawa

Yoshimitsu Shimojo

Hiromitsu Nakayama

Kiwamu Watanabe

Tatsuhiro Suzumura

Masashi Jobashi

Akihiro Oue

Shuji Michinaka

Satoshi Takekawa

Atsushi Masuda

Shinichiro Koto

Atsushi Matsumura

Masatoshi Sekine

Shunichi Ishiwata

Hiroaki Nishi

Takanao Amatsubo

Shuo Nomura

A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.

Radio communication device and semiconductor integrated circuit device used for the same

A moving image compression-coding device has a pixel determination module configured to determine whether a color of each pixel in a macro block having a plurality of pixels in an input image is a predetermined color, a pixel counter configured to count a number of the pixels having the predetermined color in the macro block, a macro block determination module configured to determine whether a color of the macro block is considered to be the predetermined color according to the count result, and a compression-coded data generator configured to compression-code the input image with a compression ratio depending on the determination result.

Moving image compression-coding device, method of compression-coding moving image, and H.264 moving image compression-coding device

The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.

Image decoding apparatus and image decoding method

An image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix, a suffix, and a syntax; a variable length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length, and, by using data contained in the bit stream and the suffix length, simultaneously decode the prefix and the suffix and output the result if the syntax selection signal selects the prefix 1 and the suffix, and decode the syntax and output the result if the syntax selection signal selects the syntax; a level formation device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and update the suffix length.

Image decoding apparatus and decoding method

An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.

Image coding apparatus and method thereof

When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced. A variable length code decoding apparatus includes an input unit which receives variable length coding data, a plurality of FIFO memories which store the variable length coding data and output or update the variable length coding data on the basis of a codeword length of the variable length coding data, a FIFO input selecting unit which outputs the variable length coding data to one of the plurality of FIFO memories, a variable length coding table storing unit which stores a variable length coding table representing a relationship between the variable length coding data, the codeword length and a decoding value, reads the variable length coding data stored in one of the plurality of FIFO memories, and compares the read variable length coding data with the variable length coding table, a table selecting unit which determines the codeword length and the decoding value on the basis of a comparison result of the variable length coding table storing unit, and outputs the determined codeword length to one of the plurality of FIFO memories, and a control unit which selects one of the plurality of FIFO memories as a destination FIFO memory, reads the variable length coding data from the input unit or one of the unselected FIFO memories, and controls the FIFO input selecting unit such that the read variable length coding data is output to the selected FIFO memory.

Variable length code decoding apparatus and variable length code decoding method

A dependent relation of operations is extracted from an operation string expressing an operation specification, and thus the dependent relation of operations is created. Connecting relations between arithmetic units constituting an initial circuit construction of a logic circuit are extracted, and thus the connecting relations of the arithmetic units and the corresponding dependent relation of operations are created. Basic conversion rules are applied to the dependent relation of operations, new conversion rules are prepared, and thus conversion rules are created. The conversion rules are repeatedly applied to the dependent relation of operations for optimization, and optimized dependent relation of operations is created. An optimized operation string is prepared from the optimized dependent relation of operations, and an optimized operation string is obtained.

High-level synthesis method including processing for optimizing arithmetic sequence of an operation string

A model of architecture of a processor is called an architecture template. Because a designer selects an architecture template of a special purpose processor which is suitable for an objective signal processing algorithm from an architecture template library, a special purpose processor which is the most suitable for any signal algorithm can be synthesized. Moreover, by providing a method of creating an architecture template simply, even if there is no desirable architecture template, an objective architecture template can be synthesized for a short time.

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Kawasaki, Japan

Yoshinori Shigeta