International Business Machines Corporation

Yoshinori Sakaue

Hideto Niijima

Takashi Toyooka

Claude Louis Bertin

Akashi Satoh

Donelli J DiMaria

Makoto Miyakawa

Hideo Asano

Kazutoshi Sugimoto

Tohru Sakakura

An improved external semiconductor memory device having a work memory for storing logical address-physical address conversion information. According to one embodiment of the present invention, a semiconductor memory device, which is connected to a host computer system and can be addressed as predetermined sector units, comprises: (a) a data storage having a nonvolatile memory that can be electrically rewritten; (b) an interface connected to the host computer system for receiving an access request; (c) volatile work memory; (d) first table preparating means for preparing a first table in the volatile work memory, by the page which consists of a plurality of sectors, for converting the requested logical sector address into a physical sector address among a physical memory space of the data storage; (e) second table preparation means for preparing a second table in the volatile work memory, by the unit which consists of a plurality of pages, for converting a logical page numbers addressed by the access request into a physical page numbers among a physical memory space of the data storage; (f) second access control means for, in response to an access request from the host computer system, referring to the second table for a unit to which the designated logical sector address belongs in order to acquire a corresponding physical page number; (g) first access control means for, in response to an access request from the host computer system, referring to the first table for a physical page to which the designated logical sector address belongs in order to acquire a corresponding physical sector address; and (h) data access means for accessing the data storage in accordance with the acquired physical sector address.

Method and apparatus for dynamically creating conversion tables to

An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.

Flash-erase-type nonvolatile semiconductor storage device

A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Three-dimensional direct-write EEPROM arrays and fabrication methods

A nonvolatile memory-with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.

Nonvolatile memory with cluster-erase flash capability and solid state

To provide an external storage system using a semiconductor memory in which the data reading and writing between the host CPU can be processed faster than the conventional magnetic disk, and only a particular sector is not frequently written and erased so that the whole memory is effectively used over a long period of time. An address control scheme was introduced in which flexibility is given to the address relation between the host CPU and the external storage and the physical address of the semiconductor memory is not one-sidedly determined by the logical address possessed by the command of the host CPU. Command processing section 34 always prepares memory blocks and sectors for writing or erasing and copying in preparation for the command processing of the host CPU, and records and holds the correspondence relation between the physical address of the selected memory block 32i or sector and the command of the host CPU in address conversion table 36. The status of memory blocks and sectors is recorded in respective managing tables 35 and 60, and used for control of processings such as writing, erasing and copying in preparation for or in response to the command of the host CPU.

External information storage system with a semiconductor memory

An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the validity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.

Method of fabricating three-dimensional direct-write EEPROM arrays

A nonvolatile memory with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.

To achieve high speed line-thinning, an electronic picture to be processed is divided into sections, and the scanning for line-thinning is performed for each section. If no point removal is performed in the scanning of a section, the line-thinning is completed for that section. When points are removed in the scanning, incomplete areas that require further line-thinning are determined based on positions where the points are removed. In the next scanning, scanning for line-thinning is not performed for all of the sections, but is done for areas within sections that contain the incomplete areas. These areas are smaller than the sections and are variably determined according to the size of their incomplete area. Thus, the area to be scanned is reduced and dynamically controlled. It is because the incomplete areas become smaller and smaller as the scanning is repeated, that the area variably determined according to the size of the incomplete area also becomes smaller. The condition to terminate all processes for line-thinning occurs when it is determined that the line-thinning is completed for all sections after checking all of them.

Growing community of inventors

Tokyo, Japan

Yoshinori Sakaue