Nec Corporation

Juniper Networks, Inc.

Nippon Electric Co., Ltd.

Yoshinori Rokugo

Rikio Maruta

Masaaki Itoh

Hisashi Sakaguchi

Hiroyuki Kikuchi

Kuniyasu Hayashi

Yasutoshi Ishizaki

Makoto Suzuki

Motoo Nishihara

Kazuo Takagi

Hiroshi Asano

Botaro Hirosaki

To provide a method and network system, wherein the proper VPI values are allocated, after the user devices are connected with the network device. A user device transmits a first specific ATM cell, while a network device receives the first specific ATM cell and transmits toward the user device a second specific ATM cell which carries a proper VPI value in the information field of ATM cell. The proper VPI value in the second specific ATM cell is memorized and used by the user device for its own VPI value for communication.

Allocating VPI for user devices

A transmission method and a network system can accommodate STM, ATM and IP in a single network by newly proposing a frame network to be used in common in physical layer and data link layer. The transmission method includes transmitting a plurality of packets in multiplexing manner, which header in each packet includes a first field holding a signal indicative of a packet length, a second field holding a signal indicative of a preferential order upon transferring the packet, a third field holding a signal indicative of a kind of traffic, a fourth field holding a signal indicative of a header length, a fifth field holding a control signal depending upon the kind of traffic, and a sixth field holding a signal indicative of a result of CRC operation of the header, a payload holding information signal depending upon kind of the traffic and a signal indicative of a result of CRC operation of the payload.

Transmission method and network system for accommodating a plurality of kinds of traffic in a common network

ATM network system and method for allocating VPI for user devices

A PLL is provided for reproducing a standard clock having a constant Jitter band from a random time information. This PLL is composed of a receiving counter - for counting the standard clock received from the transmitting side; a subtractor - for comparing between the count value of the receiving counter - which is read out each time when the receiving counter receives the count value from the transmitting counter; a differential time calculator for calculating a difference between the present count value and the preceding count value of the receiving counter; a first attenuator - for attenuating the output of the subtractor; a second attenuator - for further attenuating the output of the first attenuator; an integrator - for integrating the output of the second attenuator based on the differential time calculated by the differential time calculator; an adder - for adding the outputs of the adder and the integrator; a converter - for converting the result of the adder into a voltage signal; and a voltage control oscillator - for outputting a signal to the receiving counter based on the input of the voltage signal converted by the converter.

PLL for reproducing standard clock from random time information

A phase-locked loop circuit comprising a received data counter for counting received clock signals reproduced according to sent data count values output from a transmitter, a subtracter for subtracting the output of the received data counter from an entered sent data count value, first and second attenuators for attenuating the output of the subtracter, an integrator for integrating the output of the second attenuator, an adder for adding the output of the first attenuator to the output of the integrator, a converter for converting the output of the adder into the corresponding voltage signal, and a voltage control oscillator that is controlled by the output of the converter and outputs a received clock signal to be supplied to the received data counter.

Phase-locked loop circuit for reproducing clock signals synchronized

A digital phase synchronous circuit includes a phase comparing circuit for outputting a count value according to the result of a phase comparison between an output signal and an externally input reference signal; a frequency regulating circuit for inputting an oscillation signal with a predetermined repetition frequency and controlling the repetition frequency according to the count value to output it as the output signal; and a controlling circuit for controlling the frequency regulating circuit to output the oscillation signal with the predetermined repetition frequency when the input of the reference signal breaks down.

Digital phase synchronous circuit and data receiving circuit including

Using positive-phase or negative-phase clocks of phase count clock Pf.sub.0, a number M of multilevel quantized phase comparators output as values quantized in multiple levels the phase differences of output signals outputted from first and second N-stage frequency dividers wherein input clocks and output clocks, respectively, of a digital PLL have been N-stage frequency divided and moreover, divided into M groups. An adder adds this phase difference information and outputs advanced pulses or delayed pulses. An N1 counter counts up in response to advanced pulses and both outputs an increment pulse and undergoes setting to initial value N1 upon counting up to 2N1. In response to delayed pulses, the N1 counter counts down, and upon counting down to '0' both outputs a decrement pulse and undergoes setting to initial value N1.

Digital phase-locked loop (PLL) having multilevel phase comparators

On transferring a tributary unit (TU) from an input frame of an input signal (10) onto an output frame of an output signal (11), a recognition circuit (14) recognizes the TU of the input frame and produces not only a location signal representative of a location of the TU in the input frame But also a sort signal representative of a sort of the TU in the input frame. A threshold determining circuit (32) determines an optimum stuff threshold value (33) in response to the sort signal to produce the optimum stuff threshold value. A write controller (15) controls writing of the TU of the input frame in a memory (12) in response to the location signal by supplying a write address signal (17) to the memory. A read controller (18) controls reading of the TU out of the memory in response to a stuff request signal (19) by supplying a read address signal (23) to the memory. A stuff execution judgement circuit (25) judges whether or not a stuff operation should be executed by comparing a phase difference between the write address signal and the read address signal with the optimum stuff threshold value. The stuff execution judgement circuit produces the stuff request signal when the stuff execution judgement circuit Judges that the stuff operation should be executed. An output transmission signal producing circuit (29, 30) produce the output signal including the TU in the output frame.

Transmission signal processing circuit which can determine an optimum

Each of primary and secondary random-walk filters has longer and shorter time constants. A multi-valued phase comparator generates a start signal if a phase error generated when an abrupt frequency change occurs exceeds a given value. In response to the start signal, the primary and secondary random-walk filters are set to the shorter time constants. A timer is started by the start signal, and upon elapse of a predetermined period of time, sets the primary and secondary random-walk filters to the longer time constants.

Fully secondary DPLL and destuffing circuit employing same

An internal frame signal producing circuit for use in a cross connection system which cross connects first bit rate signals, each produced by multiplexing m second bit rate signals at first or the second bit rate signal levels, the first bit rate being higher than the second bit rate, an internal frame frequency is predetermined to be equal to a frequency f.sub.h ' higher than a first nominal frequency f.sub.h of the first bit rate digital signals by a predetermined value, the frequency f.sub.h ' being synchronized with a second nominal frequency fl of the second bit rate digital signals. In order to obtain the internal frame signal, from m second bit rate signals, the m second bit rate signals are stuff-synchronized processed to produce m stuff-synchronized signals, each having a stuff bit, a variable bit, and vacant bit at suitable bit intervals in a frame of a frame length. The m stuffed-synchronized signals are serially arranged to make the internal frame signal. In order to compensate a frequency difference between f.sub.h ' and fl, one frame consisting of all vacant bits is assigned at predetermined frame intervals.

Cross-connection network using time switch

In a cross-connection network, a plurality of asynchronous input digital signals can be cross-connected to a plurality of output lines by use of time switch. The input digital signals are pulse stuffed at a common higher bit rate and are synchronized to one another by attaching extra bits. The pulse stuffed signals are assigned into serial frames in a predetermined order by the multiplex technique and are interchanged from one to another by the time switch in the time division fashion. The frame-interchanged signal is demultiplexed to reproduce the pulse-stuffed signals which are sent out to the respective output lines assigned to the frames after removing extra bits. When the input digital signals are of higher order group, each of the higher order group digital signals is demultiplexed to lower order group signals which are pulse stuffed to be synchronized to the common higher bit rate. The pulse stuffed lower order signals are rearranged by the multiplex technique to reform each of the high order group signal which is synchronized to one another. The reformed higher order group signals are assigned in serial frames and are processed in the similar manner as described above. The frame-interchanged signals are reversely processed to be separated, demultiplexed, destuffed, and multiplexed to reproduce the input signals as the output signals.

In a destuffing circuit for use in processing an input pulse sequence comprising data pulses, stuffing pulses, and control pulses into an output pulse sequence with reference to a data pulse timing signal, the output pulse sequence is produced with the stuffing and the control pulses removed from the input pulse sequence. A local signal producing arrangement produces a local signal by digital processing a predetermined one of first through M-th timing sequences derived from the data pulse timing signal and a preselected one of first through M-th local sequences derived from the local signal, where M represents a predetermined number. The destuffing circuit further comprises a destuffing arrangment responsive to the input sequence and produces the output pulse sequence by using the data pulse timing signal and the local signal.

Destuffing circuit with a digital phase-locked loop

On multiplexing a predetermined number of lower-order multiplex digital transmission signals of a common frame period into a higher-order multiplex digital communication signal, an identification pattern (X, Y, Z) is inserted in each frame of each transmission signal. The identification patterns are specific to the respective transmission signals. The identification patterns in each frame period of the respective transmission signals are multiplexed into a single pattern (I1x, I2x, I3x, I1y, I2y, I3y, I1z, I2z, I3z) in the communication signal and used to indicate lower-order multiplex digital signal receivers to which the respective transmission signals should be directed. After the communication signal is demultiplexed into lower-order multiplex digital reception signals, the identification patterns are detected with frame synchronism established between the lower-order transmission and reception signals. Each identification pattern may consist of a preselected number of binary bits where two to the power of the preselected number should not be less than the predetermined number.

Higher-order multiplex digital communication system with identification

It has now been confirmed as regards a stuff (justification) synchronization device for each of plesiochronous input pulse sequence to be time division multiplexed that a low frequency jitter component appears in a synchronous output pulse sequence from the effect of sampling phase lags of read pulse sequences for reading the output pulse sequence for stuffing from an elastic memory (36) of the device relative to write pulse sequences for storing the input pulse sequence in the memory at a sampling interval equal to the memory capacity. The jitter is reduced (1) by selecting a prime number, preferably thirteen and more preferably seventeen or nineteen, as the memory capacity, (2) by cyclically using selected write and read pulse sequences for phase lag monitoring, or (3) by rendering the sampling interval either random or equivalently random.

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Tokyo, Japan

Yoshinori Rokugo