Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Reneasa Technology Corp.

Yoshinori Okumura

Shuichi Ueno

Atsushi Hachisuka

Masao Nagatomo

Hideaki Arima

Ikuo Ogoh

Shigenobu Maeda

Shigeto Maegawa

Takashi Kuroi

Katsuyuki Horita

Kaoru Motonami

Masayoshi Shirahata

Haruo Furuta

Takayuki Matsukawa

Tomonori Okudaira

Hideki Genjo

Tatsuya Ishii

Tomohiro Yamashita

Natsuo Ajika

Hiroji Ozaki

Wataru Wakamiya

Yasushi Matsui

Yuichi Nakashima

Kohjiroh Yuzuriha

Hiroki Shimano

Shigeru Kusunoki

Hirokazu Sayama

Kazuyuki Sugahara

Tatsuhiko Ikeda

Chikayoshi Morishima

Masahiro Yoneda

Akihiko Ohsaki

Masahiko Takeuchi

Shinya Soeda

Atsuhiro Fujii

Hideki Genjou

A width and a thickness of a bit line are represented as Wand T, respectively, a thickness of a digit line is represented as T, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L. A width of the digit line is represented as W, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L. The distances Land Land the cross-sectional areas Sand Sare set in such a manner that when L/L1, a relation of (&#x2153;)&#xb7;(L/L)&#x2266;S/S&#x2266;1 is satisfied and when L/L&#x2266;1, a relation of 1&#x2266;S/S&#x2266;3(L/L) is satisfied.

Magnetic memory device

A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2&#x2267;1, a relation of (&#x2153;)&#xb7;(L1/L2 )&#x2266;S2/S1&#x2266;1 is satisfied and when L1/L2&#x2266;1, a relation of 1&#x2266;S2/S1&#x2266;3(L1 /L2) is satisfied.

A width and a thickness of a bit line are represented as Wand T, respectively, a thickness of a digit line is represented as T, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L. A width of the digit line is represented as W, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L. The distances Land Land the cross-sectional areas Sand Sare set in such a manner that when L/L&#x2267;1, a relation of (&#x2153;)&#xb7;(L/L)&#x2266;S/S&#x2266;1 is satisfied and when L/L&#x2266;1, a relation of 1&#x2266;S/S&#x2266;3(L/L) is satisfied.

In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more than one stages. Since doses of nitrogen are different from each other between gate electrodes ( A to C) of N-channel type MOS transistors (T to T ), concentrations of nitrogen in the nitrogen-introduced regions (N to N ) are accordingly different from each other. Concentrations of nitrogen in the gate electrodes are progressively lower in the order of expected higher threshold values.

Method of manufacturing field effect transistors

P wells ( ) having different impurity profiles are adjacently formed in a surface ( S) of a semiconductor substrate ( ). A P-type layer ( ) having lower resistivity than the P wells ( ) is formed in the surface ( S) across the P wells ( ), so that the P wells ( ) are electrically connected with each other through the P-type layer ( ). Contacts ( ) fill in contact holes ( H H ) formed in an interlayer isolation film ( ) respectively in contact with the P-type layer ( ). The contacts ( ) are connected to a wire ( ). The wire ( ) is connected to a prescribed potential, thereby fixing the P wells ( ) to prescribed potentials through the contacts ( ) and the P-type layer ( ). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.

Semiconductor device

A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electric characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed is provided. An active layer is formed by performing an additional impurity injection on a part where a sidewall insulating film is removed in a forming portion of a shared contact plug. An insulating film is laminated in a high voltage circuit part and a sidewall insulating film of wide width is formed. According to this, a forming width of a sidewall insulating film can be made small in a MOS transistor for a memory cell part, and a forming width of a sidewall insulating film can be made large in a MOS transistor for a high voltage circuit part. Thereupon, in the high voltage circuit part, a source/drain active layer can be formed in the position more distant from a gate electrode.

Semiconductor device and manufacturing method thereof

An object is to prevent protrusion of a plug from an interlayer insulating film to prevent formation of a step between circuit parts exceeding a step height allowed in a planarization process and also to prevent formation of particles due to a protruded plug. An interlayer insulating film ( ) is etched back over the entire surface under an etching condition in which the etching selectivity of a polysilicon plug ( ) with respect to the interlayer insulating film ( ) is 10, for example, to recess the polysilicon plug ( ) to a given depth in a bit line contact hole ( ) to form a recessed polysilicon plug ( ).

Recessed plug semiconductor device and manufacturing method thereof

A semiconductor device manufacturing method for manufacturing a semiconductor device of constant finished dimensions as designed even when a material which is difficult to increase etch selectivity to a silicon film in a gate electrode or wiring structure is used for an anti-reflection coating, and which is also capable of achieving finer patterning through the use of a silicon oxide film or the like as a hard mask. For example, a silicon oxy-nitride film and a silicon oxide film are used for an anti-reflection coating and a hard mask, respectively, to provide etch selectivity therebetween. In etching of the anti-reflection coating and the hard mask, the hard mask such as a silicon oxide film is not completely etched in order to leave a non-single crystalline silicon film covered, under which condition the anti-reflection coating is removed.

Method of manufacturing semiconductor device

An SRAM of the present invention comprises a plurality of memory cells, which are formed over a plurality of wells, which store data and which do not have a well contact region for fixing the potential of the wells, and a plurality of well contact cells for fixing the potential of the wells that are formed over the plurality of wells so as to adjoin the memory cells, wherein the areas of the memory cells and the areas of the well contact cells are equal.

Static-type semiconductor memory device

According to a semiconductor device and a method of manufacturing the same, a trade-off relationship between threshold values and a diffusion layer leak is eliminated and it is not necessary to form gate oxide films at more than one stages. Since impurity dose are different from each other between gate electrodes ( A to C) of N-channel type MOS transistors (T to T ), impurity concentration in the gate electrodes ( A to C) are different from each other. The impurity concentration in the gate electrodes are progressively lower in the order of higher threshold values which are expected.

Semiconductor device having control electrodes with different impurity concentrations

In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.

Semiconductor device and method of manufacturing the same

Provided are a semiconductor device that can obtain more output current without increasing the occupied area of a MOS transistor, and a method for manufacturing the same. MOS transistors (M M ) are electrically isolated by a trench isolation oxide film ( ). The MOS transistor (M ) has a groove portion (GP) in which the width of the top is 20 nm to 80 nm and the depth is 50 nm to 150 nm. The groove portion (GP) is disposed at the boundary part between a trench isolation insulating film ( ) and an active region (AR ) so as to surround the active region (AR ). A gate electrode ( A) is not only disposed above the active region (AR ) but also buried in the groove (GP) with a gate oxide film ( ) interposed therebetween. Similarly, in the MOS transistor (M ), a groove portion (GP) is disposed at the boundary part between the trench isolation insulating film ( ) and an active region (AR ) so as to surround the active region (AR ), and a gate electrode ( A) is also buried in the groove (GP) with the gate oxide film ( ) interposed therebetween.

The semiconductor device has a triple well structure. The triple well and other wells have impurity concentration distributions in the depth direction, which are determined in accordance with required function. Thereby, the required performances such as suppression of a leak current can be achieved even in a miniaturized structure.

A semiconductor device and manufacturing method are provided in which an increase in contact resistance between a plug and a semiconductor layer and an increase in junction leakage current in a semiconductor layer to which a plug is connected can be prevented and fabrication cost and device area can be reduced. A multi-layer film comprising a metal layer (,), a barrier metal layer (,), a polysilicon layer (,), and a barrier metal layer (,) is patterned by photolithography and etching to form poly-metal bit lines (,) electrically connected to buried layers (,A,,B) and polysilicon plugs (,).

A nonvolatile semiconductor memory device includes an n-type region which is in contact with n,drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n,drain diffusion region, n-type region and p,impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

Growing community of inventors

Hyogo, Japan

Yoshinori Okumura