Nissan Motor Company Limited

Fuji Electric Co., Ltd.

Sanken Electric Co., Ltd.

Kao Corporation

Johns Hopkins University

National Cancer Center Research Institute

Other

Renesas Electronics Corporation

The University of Tokyo

Sumitomo Metal Mining Company, Ltd.

Thk Co., Ltd.

Murakami, Yoshinori

Yoshinori Murakami

Shinji Sato

Satoshi Tanimoto

Yusuke Zushi

Kohei Matsui

Tetsuya Hayashi

Teruyoshi Mihara

Roger Harper Reeves

Hideaki Tanaka

Masakatsu Hoshi

Saichirou Kaneko

Tsutomu Matsushita

Kenji Yao

Fumiki Kato

Hidekazu Tanisawa

Hiroshi Sato

Akira Suzuki

Hiroaki Mochizuki

Koji Maeda

Takeshi Ito

Yasuhiko Kitajima

Hajime Fukushima

Kazuhiko Kato

Kazuhiro Mitamura

Hiroomi Kuribayashi

Takao Hamakubo

Akito Kaneko

Shigeto Kayane

Kazushi Oshino

Taku Kanaoka

Hiroko Iwanari

Takashi Iseki

Manabu Tonomura

Norihiko Kiritani

Hidetake Fujinaka

Yoshiyuki Muroi

Yui Takahashi

Mitsuyoshi Kashiwagi

Hidenori Yoshida

Kazuma Ohkura

Hiroki Takahashi

Masato Takamori

Yoshitaka Yanou

Yu Fukushima

Kazuhiko Tani

Hitoshi Fukuma

Yoshiro Oishi

Tadashi Matsuhira

Kenichi Koui

Reiji Abe

The present invention provides an antibody recognizing a v9 fragment of the cell adhesion molecule CADM1.

CADM1 V9-recognizing antibody

A clamper mechanism for a motion guide device includes a clamper block having tapered faces, clamper rolling elements arranged between the tapered faces and both left and right side faces of a track member, and a clamper rolling element holder attached to the clamper block with an interposition of an elastic member. When an elastic force exerted by the elastic member acts in a direction in which the clamper block and the clamper rolling element holder are separated from each other, the clamper rolling elements bite the tapered faces to bring the clamper block into a state restrained to the track member. When an external force against the elastic force exerted by the elastic member acts, the clamper rolling elements are brought into a free state within the tapered faces to bring the clamper block into a state not restrained to the track member to exert a stable clamping force.

Clamper mechanism for motion guide device

A semiconductor device includes a semiconductor chip provided inside with a p-n junction, an opaque sealing resin covering a surface of the semiconductor chip, and a functional region arranged between the semiconductor chip and the sealing resin and configured to prevent light, which is generated when a forward current flows through the p-n junction and has a particular wavelength causing deterioration of the sealing resin, from reaching the sealing resin.

Semiconductor device

An object of the present invention is to stabilize and strengthen the strength of a bonding part between a metal electrode on a semiconductor chip and metal wiring connected thereto using a simple structure. Provided is a semiconductor device including a metal layeron a surface of a metal electrodeformed on a semiconductor chip, the metal layerconsisting of a metal or an alloy different from a constituent metal of the metal electrode, metal wiringis connected to the metal layervia a bonding part, wherein the constituent metal of the metal layeris a metal or an alloy different from the constituent metal of the metal electrode, and the bonding parthas an alloy region harder than the metal wiring

Bonding pad structure of a semiconductor device

In a heat insulating load jigof the present invention, a solder materialhaving a melting point or a solidus temperature in a range between a thermal resistance temperature of a semiconductor chipand a temperature 100&#xb0; C. below the thermal resistance temperature is interposed between a circuit boardand the semiconductor chip; a heat insulating bodyis placed on an upper side of the semiconductor chipin this state; a metal weightis disposed on the heat insulating body; and load is applied to the semiconductor chipwhile the solder materialis melted and solidified.

Method for manufacturing semiconductor device, heat insulating load jig, and method for setting up heat insulating load jig

A false report on appearance inspection of a semiconductor device is prevented by suppressing variation in surface state of an electrodeposited gold electrode. In formation of an electrodeposited gold electrode, an electrodeposited gold electrode comprised of a plurality of electrodeposited gold layers in the stack is formed by alternately repeating a step of performing energization between an anode electrode and a cathode electrode provided in a treatment cup of a plating apparatus to cause crystal growth of an electrodeposited gold layer (energization ON), and a step of performing no energization between the anode electrode and the cathode electrode (energization OFF). Consequently, even if aging variation occurs in composition of the plating solution, variation in surface state of the electrodeposited gold electrode is suppressed, and a surface state with a surface roughness of, for example, about 0.025 rad can be maintained.

Method of manufacturing semiconductor device

A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.

Method for manufacturing semiconductor device, and semiconductor device

A semiconductor module has a pair of semiconductor devices, a heat sink, a first electrode, an output electrode and a second electrode. The semiconductor devices are connected in series with each other and have first terminals that are electrically connected to a first power system and a second terminal that is electrically connected to a second power system. The first electrode is electrically connected both to one of the first terminal and to an electrode of one of the semiconductor devices. The output electrode is electrically connected both to the second terminal and to an electrode of the other of the semiconductor device. The second electrode is electrically connected to the other of the first terminals. The second electrode is connected to the heat sink via a first insulating member. The output electrode is connected to the second electrode via a second insulating member.

Semiconductor module

A switching circuit includes: a first switching element (Q); a resistor () inserted between a control electrode (G) of the first switching element (Q) and a control circuit () switching the first switching element (Q); and a first capacitor () and a second switching element () connected in series between the control electrode (G) of the first switching element (Q) and a low potential-side electrode (S) of the first switching element (Q). A high potential-side electrode of the second switching element () is connected to the control electrode (G) of the first switching element (Q). An electrode of the first capacitor () is connected to the low potential-side electrode (S) of the first switching element (Q). A control electrode of the second switching element () is connected to an electrode of the resistor () connected to the control circuit ().

Switching circuit and semiconductor module

A semiconductor device includes: a semiconductor chip including: a first main face having an edge portion, a second main face locating the opposite side to the first main face, a crystalline defect region present within a region including at least the edge portion being adjacent to the first main face, the crystalline defect region being configured to have lower stress than the stress in the other semiconductor region for the same strain; and a metallic substrate to be bonded via a bonding member to the first main face of the semiconductor chip.

Semiconductor device and method of manufacturing the same

Provided is a dentifrice which exhibits sufficient shape retentivity even when a polymer-based binder is not incorporated, which does not leave a taste or white residues even when the amount of powder incorporated is small, and which has satisfactory dispersibility in the oral cavity and a light feeling of use. A dentifrice containing the following components (A), (B) and (C):

Dentifrice

The invention provides an oral preparation or a chewing gum comprising an organic acid and/or inorganic acid and a fluoride ion supplying compound, wherein a light scattering layer is formed inside enamel of the teeth when the oral preparation or the chewing gum is applied to teeth. An internal tooth colored layer in the enamel is masked by the light scattering layer, and a white appearance is imparted to the teeth.

Oral preparation and chewing gum

Methods are provided for detecting a cell proliferative disorder associated with TSLC1 by contacting a proliferating cell of a subject suspected of having the disorder with a reagent that detects TSLC1 and detecting the level of TSLC1 in the proliferating cell. TSLC1 is a single gene whose expression is reduced or absent in A549 and some other NSCLC, hepatocellular carcinoma and pancreatic cancer cell lines. It has further been discovered that TSLC1 expression or suppression is perfectly correlated with promoter methylation state. Restoration of TSLC1 expression to normal or higher levels is sufficient by itself to suppress tumor formation. The invention further provides methods of treating such disorders by contacting cells of a patient suffering from the disorder with a therapeutically effective amount of a reagent that modulates TSLC1 level in the proliferating cells.

Diagnosis and treatment of tumor-suppressor associated disorders

A semiconductor package has: a semiconductor chip having first and second main electrodes arranged on two principal surfaces being opposite to each other; a first main wiring plate connected to the first main electrode and having a first external connection terminal; a second main wiring plate connected to the second main electrode and having a second external connection terminal; a first shell connected through an insulating film to at least a part of a second principal surface of the first main wiring plate, the second principal surface of the first main wiring plate being opposite to a first principal surface of the first main wiring plate that is connected to the first electrode; and a second shell connected through an insulating film to at least a part of a second principal surface of the second main wiring plate, the second principal surface of the second main wiring plate being opposite to a first principal surface of the second main wiring plate that is connected to the second electrode. The first principal surfaces of the first and second main wiring plates are adjacent to and parallel to each other except at the locations where the first and second main wiring plates are connected to the semiconductor chip and the locations where the first and second external connection terminals are formed.

Semiconductor package

A high voltage semiconductor device having a high current gain hFE is formed with a collector region () of a first conduction type, an emitter region () of the first conduction type, and a base region () of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region () where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region ().

Semiconductor device and manufacturing method thereof

Growing community of inventors

Tokyo, Japan

Yoshinori Murakami