Renesas Technology Corp.

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Other

Hitachi Microcomputer System, Ltd.

Yoshinori Miyaki

Hiromichi Suzuki

Kazunari Suzuki

Kunihiko Nishi

Kunihiro Tsubosaki

Fujio Ito

Takafumi Nishita

Akihiko Kameoka

Tsuyoshi Kaneda

Takahiro Naito

Sueo Kawai

Daisuke Omoda

Yukinori Tashiro

Masaru Yamada

Hirohito Ohashi

Yujiro Kajihara

Takashi Sato

Yoshiaki Sato

Hisashi Shiota

Shigezumi Matsui

Motoo Suwa

Yoshihiko Shimanuki

Junichi Arita

Toru Hayashi

Takanobu Naruse

Ryoichi Sano

An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.

Method of manufacturing semiconductor device

To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.

To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires.

Semiconductor device and method of manufacturing the same

In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chipand a resin is enlarged by making the external size of a die padsmaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chipshaving different external sizes can be mounted on the die padby cutting the leading ends of leadsto a suitable length in accordance with the external sizes of the semiconductor chips

Leadframe semiconductor integrated circuit device using the same, and method of and process for fabricating the two

The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.

Method of manufacturing a semiconductor device

A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.

An electronic circuit includes a first semiconductor device and a second semiconductor device on a mounting substrate. The mounting substrate lines have lengths which are made unequal for respective bits. Assembling lines which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. The unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines.

Electronic circuit, a semiconductor device and a mounting substrate

A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 &#x3bc;m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.

Semiconductor integrated circuit device and method of manufacturing the same

A method of manufacturing a thin, small-sized, inexpensive, non-leaded, resin-sealed type semiconductor device is disclosed. A flexible tape having plural terminals peelably through a first adhesive in a product forming portion formed on a main surface of the tape is provided, a semiconductor element is fixed to the main surface of the tape peelably through a second adhesive, electrodes formed on the semiconductor element and the terminals are connected together through conductive wires, an insulating resin layer is formed in an area including the semiconductor element and the wires on the main surface of the tape to cover the semiconductor element and the wires, and the tape on a back surface of the insulating resin layer is peeled, allowing the terminals to be exposed to the back surface of the insulating resin layer. Exposed surfaces of the terminals are each formed by a gold layer. The terminals each comprise a main metal layer of copper foil and one or plural auxiliary metal layers formed on each of a main surface and a back surface of the main metal layer. The auxiliary metal layer(s) on the main surface of the main metal layer is (are) formed using a material which affords a rough surface, thereby roughening the main surface side of each terminal.

Manufacturing method of a semiconductor device utilizing a flexible adhesive tape

A semiconductor device which can meet the requirement for a further increase in pins, which multi-functionalization and faster operation would entail is to be provided. Bonding pads and bonding pads are arranged in a zigzag pattern in a direction along an outer circumference of a main surface of a chip. To focus on power supply-line bonding pads among all the bonding pads, an odd number of bonding pads are to be arranged in a direction of the outer circumference of the main surface between adjoining bonding pads. A greater width is secured for the power supply-line bonding pads than for other bonding pads, and a diameter of wires to be connected to the power supply-line bonding pads is set greater than that of other wires.

Semiconductor device and manufacturing method of them

Growing community of inventors

Tachikawa, Japan

Yoshinori Miyaki