Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubishi Electric Engineering Company, Limited

Other

Renesas Electronics Corporation

Yoshinori Matsuura

Hiroshi Segawa

Tetsuya Matsumura

Satoshi Kumaki

Kazuya Ishihara

Atsuo Hanami

Shinichi Masuda

Toyohiko Yoshida

Shinichi Nakagawa

Shinichi Uramoto

Vasily Moshnyaga

Stefan Scotzniovsky

A time zone start time point calculating unit calculates a time zone to be set in a VOBU in accordance with audio bit rate. A time zone comparing unit compares a time point at which an audio pack is to be multiplexed with the time zone calculated by the time zone start time point calculating unit. A flag setting unit sets whether the audio pack is to be completed or not in accordance with the result of comparison by the time zone comparing unit. Therefore, a completing process takes place before a VOBU boundary, and a completed PCK will not be generated immediately after the VOBU boundary. Thus, generation of a buffer overflow can be prevented.

Multiplexing method preventing overflow of audio decoder buffer

System multiplexing apparatus preventing overflow of audio decoder buffer

The stream converting apparatus includes a stream extracting circuit that extracts a second level data stream from a first format data stream, an error detecting circuit that detects an error included in the second level data stream output from the stream extracting circuit, a data correcting circuit that corrects the detected error to generate a proper-form second level data stream, and a multiplexer that multiplexes the corrected second level data stream to generate a second format data stream.

Stream converting apparatus that converts data stream of first format possibly containing error into correct data stream of second format

The control circuit controls output of template block data held in the input section such that a plurality of operation units within the operation section are provided with data of unadjacent template blocks that are different from each other. The operation units within the operation section detect motion vectors according to the template block data provided thereto. Thus, motion vector detection in the template blocks except for those in a region on a display screen requiring no motion vector detection is distributed in the plurality of operation units. Accordingly, the motion vector search can be performed in a wider range in a vertical or horizontal direction than in the conventional case within the same operation time.

Motion vector detecting device improved in detection speed of motion vectors and system employing the same devices

To provide an image compression coding apparatus and method capable of minimizing a deterioration in picture quality which is caused on a reproduced image during an overflow of an output buffer. A picture top detector (A) executes a picture top detection processing for discarding image compression data (S) until a top of a picture of the image compression data (S) is detected during detection of a start address, and restarts a normal operation after detecting the top of the picture. A processor () brings a detection start register () into a set state and causes the picture top detector (A) to execute the picture top detection processing during an overflow of an output buffer (), and executes an interruption processing of rewriting, as a value of a write address register (), an address where a top of an overflow picture to be a picture causing the overflow is stored.

Image compressing coding apparatus and method for detecting a top position of an image in a buffer overflow

A motion estimation method capable of setting an optimum threshold value and allowing high speed processing includes the steps of: sequentially selecting one of blocks to be searched from a search range; sequentially calculating a difference between corresponding sample values of a reference block and one of blocks to be searched and accumulating an absolute value of difference; comparing an intermediate result of an accumulation value and a prescribed threshold value for a prescribed number of samples and interrupting the step of accumulating the absolute value of difference when the intermediate result exceeds the prescribed threshold value; and making one of blocks to be searched having a minimum final result of the accumulation value correspond to the reference block. The prescribed threshold value is dependent on the reference block. It is noted that the motion estimation apparatus is also disclosed.

Motion estimation method and apparatus for interrupting computation which is determined not to provide solution

Element processors (PE to PE ) included in a processor array ( ) store pixel values of a search window, shifting them forward. Further, only hatched element processors (PE , PE , PE , PE , PE , PE , PE , PE ) store pixel values of a template block, and compare them with the pixel values in the search to evaluate a similarity of pixel values. In other words, the pixel values of the template block are skipped and the pixel values which are left after skipping are compared. Therefore, it is possible to cut a hardware volume.

Motion vector detecting device

Disclosed is an image coding method and apparatus for preventing a coding quantity of coding data from being increased when a redundancy between image planes is low. A selector outputs either an optimum motion vector output from a motion vector detecting device or a motion vector output from a motion vector storing section to a real time image coding device for performing coding on the basis of an evaluation value output from the motion vector detecting device. If it is decided, according to the evaluation value, that a redundancy between a reference image plane and a coding object image plane is low, the motion vector is selected so that the coding quantity of the coding data can be prevented from being increased.

Image coding method and apparatus

An evaluation value operation part computes evaluation values of a template block and a search window block in accordance with respective ones of a plurality of predictive modes in parallel with each other, and a candidate vector determination part decides candidate vectors indicating optimum vectors in accordance with the computed evaluation values and on the basis of priority levels from a priority generation part. In accordance with these candidate vectors, an optimum vector decision part decides the optimum vectors for the respective predictive modes. Thus provided is an image coding system which can reduce the amount of codes of motion vectors with excellent picture quality.

Motion vector detector

An object of the present invention is to improve visual picture quality. A picture signal is divided into a plurality of macro blocks and coding is conducted in macro block units. The coding is conducted including quantization process by a quantization portion. A motion compensation portion outputs the quantity of motion, L, in macro block units. An average quantity of motion, L.sub.ave, of a reference picture stored in a frame memory is outputted from a division portion. A control portion compares the quantity of motion L with two reference values relative to the average quantity of motion L.sub.ave and makes a correction to lower the quantization step in the quantization portion for macro blocks whose quantity of motion L is between the reference values. Accordingly, picture quality is improved in part of picture where motion is small and deterioration of visual picture quality is noticeable. At the same time, since the correction is not applied to picture with such slow motion that deterioration of picture quality is small, redundancy of coded signal does not unnecessarily increase.

Picture coding device where the quantization step is adjusted in

It is an object of the present invention to realize bypass of input data in a macro-cell such as a FIFO memory etc. to facilitate test and evaluation about other macro-cells. A bypass route (6) is provided between an input port (DI) and an output port (DO) in a FIFO memory (1) and a data bypassing selector (8) is further provided for selecting the bypass route (6) and a sense amplifier (7) of a read bit line (R.BL). Then, in the test mode, a first selector control signal (S) is set to an L level and a second selector control signal (S) of opposite phase is set to an H level. Thus, in the test mode, a data inputted from the input port (DI) is outputted from the output port (DO) by way of the bypass route (6) without via memory cells (MC1-MCX).

Semiconductor storage device with macro-cell with monitoring of input

A data bus has a bit length of 2 words, and is divided into two bit groups, each of which corresponds to one word. Therefore, the data bus can simultaneously transfer data of two words. A register, a data operation part of a CPU, a RAM and a ROM is connected to the data bus. Even if there is generated data of two words to be transferred in these registers, the data operation part, the RAM and the ROM, the data bus can simultaneously transfer the data. In order to prevent conflict of data on the data bus, there are provided a bus driver, a multiplexer and a bus selector.

Data transfer system

A logic circuit outputs a logic signal in response to set inputs and a reset input. This logic signal is applied to output terminals through a latch circuit. When outputs Q and Q of the RS flip-flop maintain a previous state, the latch circuit is activated by a control signal applied from an OR gate to hold a previous logic signal received from the logic circuit. Thus, the logic circuit and latch circuit are arranged on a signal path from input terminals to output terminals. These logic circuit and latch circuit do not include a series connection of transistors and, therefore, is operable at high speed in response to the inputs. Consequently, the outputs Q and Q have excellent response characteristics relative to the set and reset inputs, to enable a high-speed operation.

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Hyogo, Japan

Yoshinori Matsuura