Nec Corporation

Elpida Memory, Inc.

Micron Technology Incorporated

Ps4 Luxco S.a.r.l.

Longitude Semiconductor S.a.r.l.

Other

Longitude Licensing Limited

Nec Electronics Corporation

Epida Memory, Inc.

Yoshinori Matsui

Toshio Sugano

Kenichi Sakakibara

Kouki Yamamoto

Taketo Maesako

Hiroaki Ikeda

Yoshiro Riho

Kiyohiro Furutani

Tetsuya Arai

Shoji Kaneko

Kazuhiko Kajigaya

John David Porter

Hitoshi Tanaka

Hiroki Takahashi

Shunichi Saito

Ki-Jun Nam

Yoshinori Haraguchi

Hayato Oishi

Tadashi Onodera

Akiyoshi Yamamoto

Takahiko Fukiage

Koji Ito

Seiji Miura

Osamu Nagashima

Shuichi Tsukada

Kazuhiko Abe

Takeo Fujii

Yasushi Matsubara

Keun Soo Song

Mototada Sakashita

Nakaba Kaiwa

Seiichi Hannai

Satoshi Morishita

Hiroshi Furuta

Hiroyuki Yamakoshi

Teppei Miyaji

Masaki Kawaguchi

Shun Nishimura

A clock generator circuit may generate internal data clock signals, such as quadrature phase clock signals, based at least in part, on one clock signal responsive, at least in part, to another clock signal. The internal data clock signals may be generated from a system clock signal responsive to a data clock signal. The internal data clock signal may be generated by sampling the system clock signal. The sampling may be performed responsive to the data clock signal. A latch may latch a state of the system clock signal responsive to the data clock signal. The latch may output the internal data clock signal.

Apparatuses and methods for generating clock signals

A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.

Apparatuses and methods for training operations

Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

Apparatuses including output drivers and methods for providing output data signals

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

Memory system and data transmission method

Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

Semiconductor device performing refresh operation in deep sleep mode

In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Memory module and memory system

A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. The cutting circuit is rendered non-conductive when each of the transistors in the first and second output circuits is rendered non-conductive.

Output buffer circuit with low sub-threshold leakage current

Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.

Semiconductor device with single ended main I/O line

Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

Semiconductor device having plural data input/output terminals configured for write test and read test operations

Growing community of inventors

Tokyo, Japan

Yoshinori Matsui