Mitsubishi Denki Kabushiki Kaisha

International Business Machines Corporation

Mitsubishi Electric Engineering Company, Limited

Sasakura Engineering Co., Ltd.

Yoshinori Inoue

Katsumi Dosaka

Masaki Kumanoya

Takahiro Komatsu

Yasuhiro Konishi

Kenji Tokami

Masaaki Imai

Roger R Schmidt

Yutaka Ikeda

Takeshi Kajimoto

Takeshi Tsukamoto

Mikio Sakurai

Yuto Ikeda

Masaki Shimoda

Takahiko Fukiage

Kazuhiro Sakemi

Masayoshi Funatsu

Jyunji Takayoshi

Hiroaki Hayase

Minoru Onai

A cooling apparatus and method are provided for facilitating cooling of an electronic apparatus that includes a semiconductor element. The cooling apparatus includes an evaporator containing a coolant and evaporating the coolant under a reduced pressure lower than an ambient pressure to generate a chilled coolant, a condenser regenerating the coolant from a vapor of the coolant and being fluid-communicated with the evaporator through a bypass line, and a circulating pump and a line supplying the chilled coolant to a heat exchange area of the electronic apparatus to conduct a heat exchange with an air flow passing though the semiconductor element at a hot side of the electronic apparatus and returning the coolant after the heat exchange to the condenser.

Facilitating cooling of an electronics rack employing water vapor compression system

In an apparatus comprising: an evaporatorfor boiling and evaporating a cold/heat evaporable liquid under a reduced pressure; a condenserfor condensing vapor; a cold/heat indirect heat exchangerat a loadside; a cooling heat exchangerusing the air; cold-heat circulation meansandfor circulating a cold/heat evaporable liquid in the evaporator to the cold/heat indirect heat exchanger; cooling circulation meansandfor circulating a cooling evaporable liquid in the condenser to the cooling heat exchanger; and a vapor compressorprovided in a vapor ductextending from the evaporator to the condenser, a running cost is reduced when a temperature at the condenser side becomes lower than a temperature at the evaporator side due to a drop in air temperature, without a rise in a temperature of the cold/heat evaporable liquid. The vapor ductis provided with a bypass vapor pathfor bypassing the vapor compressor. The bypass vapor path is provided with an on-off valve. When a temperature at the condenser side becomes lower than a temperature at the evaporator side, the vapor compressor is shut down and the on-off valve is opened.

Liquid evaporation cooling apparatus

A semiconductor memory device has pads, a source voltage supplying circuit, and a memory cell array. The source voltage supplying circuit includes an output node, a switching circuit, and a node. In a normal operation mode, the switching circuit is turned off, and the source voltage supplying circuit supplies a ground voltage supplied from the pad directly to the memory cell array. In a test mode, the switching circuit is turned on, and the source voltage supplying circuit supplies the ground voltage applied from the pad to the memory cell array via an impedance. As a result, a memory cell having little margin can be easily detected.

Semiconductor memory device capable of detecting memory cell having little margin

When input signal IN rises to an 'H' level, node N1 attain an 'H' level, and output terminal OUT is charged to a level of VCC-V.sub.TH by n channel transistor. Capacitor is charged by the 'H' level signal transmitted through inverters, and the charged potential is superimposed on output terminal OUT. When a short pulse is merged with input signal IN, RS flipflop is latched, and node N1 attains an 'L' level, thereby discharging the voltage of the output terminal. When the output terminal attains an 'L' level, NAND gate is opened and RS flipflop is reset, thereby raising the output terminal again to a boost voltage.

Boost circuit

In a semiconductor memory, bit data read out of a memory cell are placed on a data line pair. The gate control circuit detects the transfer of the bit data to the data line pair and activates the control signal. The active control signal turns on the transfer gates located between the data line pair and the output buffer circuit so that the bit data are transferred and held by the latch circuits. The output buffer circuit releases output data represented by the latched bit data to the outside by way of the data input/output pin. This arrangement and operation eliminate the floating state of external output data and extend the duration of valid external output data in one operation cycle.

Semiconductor memory having extended data out function

A transfer gate is provided between an input terminal, receiving voltage Vh of the super Vcc level when a special operating mode is set, and an inverter and an n channel MOS transistor included in a super Vcc detection circuit of a DRAM. The transfer gate is rendered conductive only during a potential detection period during which signal WCBR attain an 'H' level. Therefore, a leakage current flowing from the input terminal through the n channel MOS transistor to a ground terminal can be minimized, thereby reducing a consumed current.

Super VCC detection circuit

A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.

Semiconductor device including signal generating circuit with level

In a DRAM, buffer circuits constituting a column address buffer are provided near address input pads receiving external address signals to be input thereto, and switch circuits arranged near the address input pads are connected between the address input pads and a row address buffer. Driving capability of each buffer circuits is set larger than in the prior art. Each switch circuit is controlled to be OFF while a column address signal is being supplied to a corresponding one of the address input pads. While the column address signal is externally applied to the address input pads, the capacitance and resistance of the interconnection layer which affects the waveform of the internal column address signal can be reduced, and hence time required for selecting one column of memory cells in each of memory cell array blocks in response to the external column address signal can be reduced, thus reducing the access time in the DRAM.

Semiconductor memory device and operating method thereof

A dynamic type semiconductor memory device includes a plurality of data input/output nodes, a plurality of /CAS buffers for generating column address strobe signals corresponding to each of said input/output nodes, and an input node carrying out only data input. A switching signal generation circuit generates first and second switching signals indicating data input/output control modes. Memory cells corresponding in number to the data input/output nodes are selected simultaneously from a memory cell array. In operation of control mode A, data input/output is effected using an input node and one data input/ouput node. In the case of control mode B, data writing/reading is effected via a plurality of data input/output nodes according to one column address strobe signal. In the case of control mode C, data input/output is carried out individually for each input/output node according to a plurality of column address strobe signals. Modes A, B and C can be realized in one DRAM. Particularly, in mode C controlling data input/output according to respective column address strobe signals, writing/reading of unnecessary data bits can be prevented to reduce power consumption and prevent erroneous parity bit writing.

Semiconductor memory device with changeable input/output data bit

The present invention relates to a memory device having reduced access time of memory cells in a test mode. The memory device forms, in the test mode, read data D.sub.R by applying Ex-OR processing to a plurality of data read from a memory cell array 11 by a data processing circuit 5, to provide the formed data to the outside through a data output circuit 6. The timing of the output of data to the outside is delayed, by delay circuit 12 in the test mode, than that in the normal operation by a time period corresponding to time required for the EX-OR processing in data processing circuit 5. Consequently, output of invalid data to the outside can be prevented, and thus access time of valid data can be reduced.

Memory device delaying timing of outputting data in a test mode as

A semiconductor memory device comprises eight memory arrays arranged in one column. A peripheral circuit is arranged in the central portion of the eight memory arrays, two column decoders being arranged with the peripheral circuit interposed therebetween. Each of the eight memory arrays is provided with a row decoder. A plurality of first column selecting lines are provided so as to cross the three memory arrays arranged on one side of the peripheral circuit from the column decoder. In addition, a plurality of second column selecting lines are provided so as to intersect with the three memory arrays arranged on the other side of the peripheral circuit from the column decoder.

Semiconductor memory device comprising a plurality of memory arrays with

In DRAM divided into plurality of blocks and operating on a block basis, each equalizing circuit is controlled such that release of equalization of an IO line pair is carried out only in a block having a memory cell from which data is to be read for data reading. Since a MOS transistor 40 provided between two IO lines constituting each IO line pair 2 for equalization of these lines and its release is not switched from on to off wastefully, current consumed for charge/discharge of a gate of the MOS transistor is considerably reduced compared to a conventional case.

Semiconductor memory device having IO line pair to be equalized and

A dynamic-type semiconductor memory device has a test mode of simultaneously carrying out functional testing on a plurality of bits of memory cells. In data writing in the test mode, data inverted from the write-in data is written in at least a 1-bit memory cell out of the plurality of bits of memory cells selected simultaneously, and the same data as the write-in data is written in the remaining memory cells. In data reading in the test mode, the data of those of the memory cells selected simultaneously, in which the inverted data is written are inverted and read, while the data of the remaining memory cells are read as they are. Logic processing is carried out on the read-out data of the plurality of bits, so that a logic value indicating acceptability of the semiconductor memory device is output, depending on a result of determination as to whether or not the read-out data is the same as each other.

Dynamic-type semiconductor memory device operable in test mode and

A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.

A semiconductor memory device comprises eight memory arrays (b 10a, 10b) arranged in one column. A peripheral circuit (60) is arranged in the central portion of the eight memory arrays (10a, 10b), two column decoders (51, 52) being arranged with the peripheral circuit (60) interposed therebetween. Each of the eight memory arrays (10a, 10b) is provided with a row decoder (20). A plurality of first column selecting lines (CL1) are provided so as to cross the three memory arrays (10a, 10b) arranged on one side of the peripheral circuit (60) from the column decoder (51). In addition, a plurality of second column selecting lines (CL2) are provided so as to intersect with the three memory arrays (10a, 10b) arranged on the other side of the peripheral circuit (60) from the column decoder (52).

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Hyogo, Japan

Yoshinori Inoue