Sharp Kabushiki Kaisha Corporation

Panasonic Corporation

Yoshinori Hashimoto

Futoshi Deguchi

Youichirou Honda

Hiroshi Kawano

Munenori Fujimura

Shuichiro Yamaguchi

Takumi Naruse

Takaaki Hirano

A transmission/reception antenna and a transmission/reception device using the antenna wherein the antenna includes a dielectric base board, an excitation loop antenna provided on the dielectric base board, a transmission/reception loop antenna provided on the dielectric base board in close proximity of but not in contact with the excitation loop antenna, and a resonance capacitor connected between two ends of the transmission/reception loop antenna. A coupling capacitor is connected to one of the two ends of the transmission/reception loop antenna. The excitation loop antenna is connected to a transmitter, and the transmission/reception loop antenna is connected to the receptor via the coupling capacitor. Thereby, the frequency property may be expanded without increasing the power consumption, and the reception processing unit is enabled to properly process the reception signal.

Transmission/reception antenna and transmission/reception device using same

Provided are a transmission/reception antenna and a transmission/reception device using the same wherein the transmission/reception antenna comprises an excitation loop antenna () having a loop of a single turn and a transmission/reception loop antenna () having a pair of loops () of a plurality of turns which are closely wound around a magnetic member (). The two loops of the transmission/reception loop antenna are located on either side of the excitation loop. A resonance capacitor () is connected across one ends of the two loops of the transmission/reception loop antenna, and a connecting portion () is connected between the ends of the two loops opposite to those connected to the resonance capacitor. The frequency property is expanded without increasing the power consumption.

A circuit module is mounted with an IC that modulates and demodulates a multicarrier signal. The circuit module has a laminated board, which is provided internally with a plurality of conductive layers laminated having insulating layers in between, and an IC, which is provided with a plurality of ground terminals to be grounded. Of the plurality of conductive layers, a conductive layer provided proximate to the IC configures a ground layer electrically connected to the plurality of ground terminals.

Circuit module and power line communication apparatus

In normal operation, an internal circuit operates in synchronism with a clock CK, so that switching operation of the output circuit is performed based on inputted data and an output enable signal. At this point, an output from the internal circuit to a three-state control circuit is forcedly set by state control circuits, whereby different test operations are performed on the output circuit.

Semiconductor device

A clock signal switching circuit, to which at least first and second clock signals and a switching signal requesting a switching operation are inputted, and which selectively outputs one of the inputted first and second clock signals by the requested switching operation, the second clock signal being synchronized with the first clock signal and having an integer multiple times cycle of the first clock signal, is provided with: a generating device, to which the second clock signal is inputted, for generating a strobe pulse at a transition timing of the inputted second clock signal; and a sampling device, to which the switching signal and the generated strobe pulse are inputted, for sampling the inputted switching signal at a timing of the inputted generated strobe pulse. The clock signal switching circuit is also provided with: a switching device, to which the first and second clock signals and the sampled switching signal are inputted, for switching to output one of the inputted first and second clock signals in correspondence with the inputted sampled switching signal.

Clock signal switching circuit

Upon power-on, a microprocessor is reset and initiates a cold start initialization program stored in ROM for initializing the microprocessor and associated peripherals. Thereafter, externally input control signals to the microprocessor indicate a desirable initialization operation for a warm start when the microprocessor is subsequently reset by an operator. A reset address generating circuit generates (1) a first address setting signal to set a first starting address of the initialization program for a cold start when receiving the reset signal at a power-ON or (2) a second address setting signal to set a second starting address of the initialization program corresponding to the warm start after the power-ON when receiving both a reset signal and a control signal generated externally by a user. A program counter is then set to an address corresponding to the inputted address setting signal. The microprocessor reads and executes initialization programs based on instructions in memory addressed by the program counter.

Microprocessor for selectively performing cold and warm starts

A counter circuit includes a plurality of one-bit counters connected in series. The counter circuit includes first and second input terminals which are supplied with a predetermined signal, respectively, in an operational test mode. The counter circuit further includes a unit for alternately supplying a carry signal to a carry signal input of each one-bit counter in series when the predetermined signals are applied thereto. The unit may be composed of a plurality of OR circuits. Each OR circuit is provided with one input connected to the carry signal output of a one-bit counter at the preceding stage of the series, the other input connected to either the first input terminal or the second input terminal, and an output connected to the one-bit counter at the next stage.

Counter circuit with or gates interconnecting stages to provide

In a sense amplifier connected to a bit line pair of a semiconductor memory device, a control gate is connected between an amplifying circuit and a transistor for activating the amplifying circuit. The control gate closes only when either of the bit lines is HIGH. When both the bit line are HIGH or LOW, the amplifying circuit does not operate.

Sense amplifier for semiconductor memory device

An integrated circuit device is provided in an integrated circuit which has an input/output terminal device for inputting a signal onto an internal input line and outputting a signal from an internal output line during a normal operation of the integrated circuit. The integrated circuit device includes a test terminal through which a test mode signal is inputted, the test mode signal being inputted when a withstand voltage test is to be performed with respect to the integrated circuit. The integrated circuit device also includes a switching device disposed between the internal input line and the input/output terminal device and between the internal output line and the input/output terminal device, to which the test mode signal is inputted from the test terminal, for electrically coupling the internal input and output lines with the input/output terminal device during the normal operation and disconnecting the internal input and output lines with the input/output terminal device when the test mode signal is inputted.

Integrated circuit for electrostatic discharge testing

A bidirectional I/O signal separation circuit for connecting a circuit device having a bidirectional I/O terminal with another circuit device having individual input and output terminals, in which an output signal of the circuit device to be connected is not supplied to an input terminal of the same circuit device, and which is able to establish a connection between a semiconductor IC device in which the logical level of a signal is used as information and a semiconductor IC device in which a pulse signal is used as information.

Growing community of inventors

Nara, Japan

Yoshinori Hashimoto