Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Yoshinori Deguchi

Akio Hasebe

Bunji Yasumura

Naohiro Makihira

Mitsuyuki Kubo

Fumikazu Takei

Kazunobu Miki

Yoshihiro Kashiba

Shigeki Maekawa

Megumi Takemoto

Akinobu Watanabe

Naozumi Morino

Susumu Kasukabe

Yasunori Narizuka

Ryo Mori

Teruaki Kanzaki

Kazuki Fukuoka

Teruo Shoji

Yoshiaki Sato

Masahiro Ueda

Akira Matsumoto

Kentaro Saito

Masahiro Tanaka

Ryoichi Takagi

Masayoshi Okamoto

Seiya Isozaki

Iwao Natori

Motoji Murakami

Mitsunobu Wansawa

In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

Method of manufacturing semiconductor device

A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line Marranged immediately below the pad PD, the wiring line Mis arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line Mbelong is formed immediately below the first region of the pad PD.

Semiconductor device and method of manufacturing the same

A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.

Semiconductor device including a pad and a wiring line arranged for bringing a probe into contact with the pad and method of manufacturing the same

To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Method for manufacturing semiconductor device

Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

Semiconductor device and manufacturing method for the same

The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.

Semiconductor device

By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

Manufacturing method of semiconductor integrated circuit device

Growing community of inventors

Tokyo, Japan

Yoshinori Deguchi