Denso Corporation

Yoshinori Arashima

Shigeki Takahashi

Hirofumi Abe

Yutaka Fukuda

Shouichi Okuda

A semiconductor device includes: a semiconductor substrate having first and second pads; an output transistor; and a current control circuit having first and second resistors, a control signal generation circuit, first and second switching circuits. The first or second resistor is disposed between the first or second pad and the output transistor. The control signal generation circuit generates a control signal to the output transistor based on a voltage of both ends of the first or second resistor. The first or second switching circuit is disposed between both ends of the first or second resistor and the control signal generation circuit. The first or second switching circuit is controlled to be in an on-state.

Semiconductor device having output transistor and current control circuit

The semiconductor output circuit of the invention has an insulated gate transistor including a first terminal, a second terminal and a gate terminal, a conductive state of the insulated gate transistor being controlled by a drive circuit connected to the gate terminal, a capacitive element and a first resistor connected in series between the second terminal and the gate terminal, and a second resistor connected between the gate terminal and the first terminal. The insulated gate transistor has a cell area formed on a semiconductor substrate, in which a plurality of unit cells each defining a unit transistor connected between the first and second terminals are laid out. The second resistor has such a resistance that all of the unit transistors defined by the unit cells are turned on uniformly when electrostatic discharge is applied to the first or second terminal.

Semiconductor output circuit

Semiconductor equipment includes a semiconductor substrate, a plurality of transistors having a source cell and a drain cell disposed alternately on the substrate, and upper and lower layer wirings for electrically connecting the source cells and the drain cells. The lower layer wiring includes a first source wiring for connecting the neighboring source cells and a first drain wiring for connecting the neighboring drain cells. The upper layer wiring includes a second source wiring for connecting to the first source wiring and a second drain wiring for connecting to the first drain wiring. A width of the second source wiring is wider than that of the first source wiring, and a width of the second drain wiring is wider than that of the first drain wiring. The second source wiring and the second drain wiring are disposed alternately.

Growing community of inventors

Gamagori, Japan

Yoshinori Arashima